📄 start.s.svn-base
字号:
mtspr HID0, r3 lis r3, CFG_HID0_FINAL@h ori r3, r3, CFG_HID0_FINAL@l SYNC mtspr HID0, r3 /* clear all BAT's */ /*--------------------------------------------------------------*/ li r0, 0 mtspr DBAT0U, r0 mtspr DBAT0L, r0 mtspr DBAT1U, r0 mtspr DBAT1L, r0 mtspr DBAT2U, r0 mtspr DBAT2L, r0 mtspr DBAT3U, r0 mtspr DBAT3L, r0 mtspr DBAT4U, r0 mtspr DBAT4L, r0 mtspr DBAT5U, r0 mtspr DBAT5L, r0 mtspr DBAT6U, r0 mtspr DBAT6L, r0 mtspr DBAT7U, r0 mtspr DBAT7L, r0 mtspr IBAT0U, r0 mtspr IBAT0L, r0 mtspr IBAT1U, r0 mtspr IBAT1L, r0 mtspr IBAT2U, r0 mtspr IBAT2L, r0 mtspr IBAT3U, r0 mtspr IBAT3L, r0 mtspr IBAT4U, r0 mtspr IBAT4L, r0 mtspr IBAT5U, r0 mtspr IBAT5L, r0 mtspr IBAT6U, r0 mtspr IBAT6L, r0 mtspr IBAT7U, r0 mtspr IBAT7L, r0 SYNC /* invalidate all tlb's */ /* */ /* From the 603e User Manual: "The 603e provides the ability to */ /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ /* instruction invalidates the TLB entry indexed by the EA, and */ /* operates on both the instruction and data TLBs simultaneously*/ /* invalidating four TLB entries (both sets in each TLB). The */ /* index corresponds to bits 15-19 of the EA. To invalidate all */ /* entries within both TLBs, 32 tlbie instructions should be */ /* issued, incrementing this field by one each time." */ /* */ /* "Note that the tlbia instruction is not implemented on the */ /* 603e." */ /* */ /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ /* incrementing by 0x1000 each time. The code below is sort of */ /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ /* */ /*--------------------------------------------------------------*/ li r3, 32 mtctr r3 li r3, 01: tlbie r3 addi r3, r3, 0x1000 bdnz 1b SYNC /* Done! */ /*--------------------------------------------------------------*/ blr/* Cache functions. * * Note: requires that all cache bits in * HID0 are in the low half word. */ .globl icache_enableicache_enable: mfspr r3, HID0 ori r3, r3, HID0_ICE lis r4, 0 ori r4, r4, HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync mtspr HID0, r4 /* sets enable and invalidate, clears lock */ isync mtspr HID0, r3 /* clears invalidate */ blr .globl icache_disableicache_disable: mfspr r3, HID0 lis r4, 0 ori r4, r4, HID0_ICE|HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync mtspr HID0, r4 /* sets invalidate, clears enable and lock */ isync mtspr HID0, r3 /* clears invalidate */ blr .globl icache_statusicache_status: mfspr r3, HID0 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 blr .globl dcache_enabledcache_enable: mfspr r3, HID0 ori r3, r3, HID0_DCE lis r4, 0 ori r4, r4, HID0_DLOCK andc r3, r3, r4 ori r4, r3, HID0_DCI sync mtspr HID0, r4 /* sets enable and invalidate, clears lock */ sync mtspr HID0, r3 /* clears invalidate */ blr .globl dcache_disabledcache_disable: mfspr r3, HID0 lis r4, 0 ori r4, r4, HID0_DCE|HID0_DLOCK andc r3, r3, r4 ori r4, r3, HID0_DCI sync mtspr HID0, r4 /* sets invalidate, clears enable and lock */ sync mtspr HID0, r3 /* clears invalidate */ blr .globl dcache_statusdcache_status: mfspr r3, HID0 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 blr .globl get_pvrget_pvr: mfspr r3, PVR blr/*------------------------------------------------------------------------------*//* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * * r3 = dest * r4 = src * r5 = length in bytes * r6 = cachelinesize */ .globl relocate_coderelocate_code: mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address * * Offset: */ sub r15, r10, r4 /* First our own GOT */ add r14, r14, r15 /* then the one used by the C code */ add r30, r30, r15 /* * Now relocate code */ cmplw cr1,r3,r4 addi r0,r5,3 srwi. r0,r0,2 beq cr1,4f /* In place copy is not necessary */ beq 7f /* Protect against 0 count */ mtctr r0 bge cr1,2f la r8,-4(r4) la r7,-4(r3)1: lwzu r0,4(r8) stwu r0,4(r7) bdnz 1b b 4f2: slwi r0,r0,2 add r8,r4,r0 add r7,r3,r03: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b/* * Now flush the cache: note that we must start from a cache aligned * address. Otherwise we might miss one cache line. */4: cmpwi r6,0 add r5,r3,r5 beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 cmpwi r7,0 beq 9f mr r4,r35: dcbst 0,r4 add r4,r4,r6 cmplw r4,r5 blt 5b sync /* Wait for all dcbst to complete on bus */9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 cmpwi r7,0 beq 7f mr r4,r36: icbi 0,r4 add r4,r4,r6 cmplw r4,r5 blt 6b7: sync /* Wait for all icbi to complete on bus */ isync/* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 blrin_ram: /* * Relocation Function, r14 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. */ li r0,__got2_entries@sectoff@l la r3,GOT(_GOT2_TABLE_) lwz r11,GOT(_GOT2_TABLE_) mtctr r0 sub r11,r3,r11 addi r3,r3,-41: lwzu r0,4(r3) add r0,r0,r11 stw r0,0(r3) bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */2: li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 addi r3,r3,-4 beq 4f3: lwzu r4,4(r3) lwzux r0,r4,r11 add r0,r0,r11 stw r10,0(r3) stw r0,0(r4) bdnz 3b4:clear_bss: /* * Now clear BSS segment */ lwz r3,GOT(__bss_start) lwz r4,GOT(_end) cmplw 0, r3, r4 beq 6f li r0, 05: stw r0, 0(r3) addi r3, r3, 4 cmplw 0, r3, r4 bne 5b6: mr r3, r9 /* Global Data pointer */ mr r4, r10 /* Destination Address */ bl board_init_r /* * Copy exception vector code to low memory * * r3: dest_addr * r7: source address, r8: end address, r9: target address */ .globl trap_inittrap_init: lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) li r9, 0x100 /* reset vector always at 0x100 */ cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ mflr r4 /* save link register */1: lwz r0, 0(r7) stw r0, 0(r9) addi r7, r7, 4 addi r9, r9, 4 cmplw 0, r7, r8 bne 1b /* * relocate `hdlr' and `int_return' entries */ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET li r8, Alignment - _start + EXC_OFF_SYS_RESET2: bl trap_reloc addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 2b li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET bl trap_reloc li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET bl trap_reloc li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET li r8, SystemCall - _start + EXC_OFF_SYS_RESET3: bl trap_reloc addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 3b li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET4: bl trap_reloc addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 4b mfmsr r3 /* now that the vectors have */ lis r7, MSR_IP@h /* relocated into low memory */ ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ andc r3, r3, r7 /* (if it was on) */ SYNC /* Some chip revs need this... */ mtmsr r3 SYNC mtlr r4 /* restore link register */ blr /* * Function: relocate entries for one exception vector */trap_reloc: lwz r0, 0(r7) /* hdlr ... */ add r0, r0, r3 /* ... += dest_addr */ stw r0, 0(r7) lwz r0, 4(r7) /* int_return ... */ add r0, r0, r3 /* ... += dest_addr */ stw r0, 4(r7) blr⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -