r2808init.c

TMS320F2808的完整驱动测试程序源码

/*H*****************************************************************************
*
* $Archive::                                                                   $
* $Revision::                                                                  $
* $Date::                                                                      $
* $Author::                                                                    $
*
* DESCRIPTION: R2808 Post
*
* GLOBALS 
*
* PUBLIC FUNCTIONS:
*                              
* PRIVATE FUNCTIONS:
*
* USAGE/LIMITATIONS:
*
* NOTES:  
*     
* (C) Copyright 2004 by Spectrum Digital Incorporated
* All rights reserved
*
*H*****************************************************************************/
#include <stdio.h>
#include "DSP280x_Device.h"
#include "r2808cfg.h"
#include "r2808init.h"

//---------------------------------------------------------------------------
// XINTF_Init() : Init the external memory system
//---------------------------------------------------------------------------                                     
void XINTF_Init( void )
{
	// Empty for F2808 or we could turn off XCLKOUT
}

interrupt void rsvd_ISR(void)          // for test
{
  
  // Stop in debug else wait for WD to cause reset
#if defined( _DEBUG )
  asm ("      ESTOP0");
#endif 
  for(;;);
}

//---------------------------------------------------------------------------
// InitSysCtrl:  Taken from DSP28_SysCtrl.c
//---------------------------------------------------------------------------
void InitSysCtrl(void)
{
	volatile Uint16 iVol;
	int      val = 10; // 100MHz

	
	// Disable watchdog module
	EALLOW;
	SysCtrlRegs.WDCR= 0x0068;
	EDIS;
	
	// Initalize PLL.  This sets the pll for x10/2 or 100MHz when using a 30
	// MHz input clock, i.e. eZdsp or VDB.
	// Make sure the PLL is not not running in limp mode
	if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1)
	{
	   if (SysCtrlRegs.PLLCR.bit.DIV != val)
	   {
	
	      EALLOW;
	      // Before setting PLLCR turn off missing clock detect
	      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
	      SysCtrlRegs.PLLCR.bit.DIV = val;
	      EDIS;
	
	      // Optional: Wait for PLL to lock.
	      // During this time the CPU will switch to OSCCLK or OSCCLK/2 until
	      // the PLL is stable.  Once the PLL is stable the CPU will 
	      // switch to the new PLL value. 
	      //
	      // This time-to-lock is monitored by a PLL lock counter.   
	      //   
	      // Code is not required to sit and wait for the PLL to lock.   
	      // However, if the code does anything that is timing critical, 
	      // and requires the correct clock be locked, then it is best to 
	      // wait until this switching has completed.  
	
	
	      // Wait for the PLL lock bit to be set.  
	      // Note this bit is not available on 281x devices.  For those devices
	      // use a software loop to perform the required count. 
	
	      while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) { }
	      
	      EALLOW;
	      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
	      EDIS;
	   }
	}
	
	// If the PLL is in limp mode, shut the system down
	else 
	{
	  // Replace this line with a call to an appropriate
	  // SystemShutdown(); function. 
	  asm("        ESTOP0");
	}
	
	EALLOW;	   
	// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
	SysCtrlRegs.HISPCP.all = 0x0001;
	SysCtrlRegs.LOSPCP.all = 0x0002;
	
	SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2;
	  	
	// Peripheral clock enables set for the selected peripherals.   
	// If you are not using a peripheral you may want to leave
	// the clock off to save on power. 
	// 
	// Note: not all peripherals are available on all 280x derivates.
	// Refer to the datasheet for your particular device. 
	
	SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;    // ADC
	SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1;   // I2C
	
	SysCtrlRegs.PCLKCR0.bit.SPIAENCLK=1;     // SPI-A
	SysCtrlRegs.PCLKCR0.bit.SPIBENCLK=1;     // SPI-B
	SysCtrlRegs.PCLKCR0.bit.SPICENCLK=1;     // SPI-C
	SysCtrlRegs.PCLKCR0.bit.SPIDENCLK=1;     // SPI-D
	
	SysCtrlRegs.PCLKCR0.bit.SCIAENCLK=1;     // SCI-A
	SysCtrlRegs.PCLKCR0.bit.SCIBENCLK=1;     // SCI-B
	
	SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1;    // eCAN-A
	SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1;    // eCAN-B
	
	SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1;  // eCAP1
	SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1;  // eCAP2
	SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1;  // eCAP3
	SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1;  // eCAP4
	
	SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;  // ePWM1
	SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1;  // ePWM2
	SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1;  // ePWM3
	SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1;  // ePWM4
	SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1;  // ePWM5
	SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1;  // ePWM6
	
	SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1;  // eQEP1
	SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1;  // eQEP2
	                    
	EDIS;

}

//---------------------------------------------------------------------------
// InitPieCtrl: Taken from DSP28_PieCtrl.c
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void InitPieCtrl(void)
{
    // Disable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;

	// Clear all PIEIER registers:
	PieCtrlRegs.PIEIER1.all = 0;
	PieCtrlRegs.PIEIER2.all = 0;
	PieCtrlRegs.PIEIER3.all = 0;	
	PieCtrlRegs.PIEIER4.all = 0;
	PieCtrlRegs.PIEIER5.all = 0;
	PieCtrlRegs.PIEIER6.all = 0;
	PieCtrlRegs.PIEIER7.all = 0;
	PieCtrlRegs.PIEIER8.all = 0;
	PieCtrlRegs.PIEIER9.all = 0;
	PieCtrlRegs.PIEIER10.all = 0;
	PieCtrlRegs.PIEIER11.all = 0;
	PieCtrlRegs.PIEIER12.all = 0;

	// Clear all PIEIFR registers:
	PieCtrlRegs.PIEIFR1.all = 0;
	PieCtrlRegs.PIEIFR2.all = 0;
	PieCtrlRegs.PIEIFR3.all = 0;	
	PieCtrlRegs.PIEIFR4.all = 0;
	PieCtrlRegs.PIEIFR5.all = 0;
	PieCtrlRegs.PIEIFR6.all = 0;
	PieCtrlRegs.PIEIFR7.all = 0;
	PieCtrlRegs.PIEIFR8.all = 0;
	PieCtrlRegs.PIEIFR9.all = 0;
	PieCtrlRegs.PIEIFR10.all = 0;
	PieCtrlRegs.PIEIFR11.all = 0;
	PieCtrlRegs.PIEIFR12.all = 0;

	// Enable PIE:
	PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
	PieCtrlRegs.PIEACK.all = 0xFFFF;
}	

//---------------------------------------------------------------------------
// InitPieVectTable: Taken from PieVect.c and sripped down
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//

void InitPieVectTable(void)
{
	int16	i;

	Uint32  Source = (Uint32)rsvd_ISR;
	Uint32 * Dest = (void *) &PieVectTable;
	
	EALLOW;	
	for(i=0; i < 128; i++)
		*Dest++ = Source;	
		
    //PieVectTable.TINT0 = Int1Isr;
	EDIS;

	// Enable the PIE Vector Table
	PieCtrlRegs.PIECTRL.bit.ENPIE = 1;	
			
}

#define CSMSCR       (volatile Uint16*)0x00000AEF   // CSM status and control register 
	
#define KEY0         (volatile Uint16*)0x00000AE0   /* low word of the 128-bit key */
#define KEY1         (volatile Uint16*)0x00000AE1   /* next word in 128-bit key */
#define KEY2         (volatile Uint16*)0x00000AE2   /* next word in 128-bit key */ 
#define KEY3         (volatile Uint16*)0x00000AE3   /* next word in 128-bit key */
#define KEY4         (volatile Uint16*)0x00000AE4   /* next word in 128-bit key */
#define KEY5         (volatile Uint16*)0x00000AE5   /* next word in 128-bit key */
#define KEY6         (volatile Uint16*)0x00000AE6   /* next word in 128-bit key */
#define KEY7         (volatile Uint16*)0x00000AE7   /* high word of the 128-bit key */
#define PWL0         (volatile Uint16*)0x003F7FF8   /* Password 0 */
#define PWL1         (volatile Uint16*)0x003F7FF9   /* Password 1 */
#define PWL2         (volatile Uint16*)0x003F7FFA   /* Password 2 */
#define PWL3         (volatile Uint16*)0x003F7FFB   /* Password 3 */
#define PWL4         (volatile Uint16*)0x003F7FFC   /* Password 4 */
#define PWL5         (volatile Uint16*)0x003F7FFD   /* Password 5 */
#define PWL6         (volatile Uint16*)0x003F7FFE   /* Password 6 */
#define PWL7         (volatile Uint16*)0x003F7FFF   /* Password 7 */

int CSM_unlock()
{
    volatile Uint16 temp;
    
    // Load the key registers with the current password
    EALLOW;
    *KEY0 = 0xFFFF;
    *KEY1 = 0xFFFF;
    *KEY2 = 0xFFFF;
    *KEY3 = 0xFFFF;
    *KEY4 = 0xFFFF;
    *KEY5 = 0xFFFF;
    *KEY6 = 0xFFFF;
    *KEY7 = 0xFFFF;   
    EDIS;

    // Perform a dummy read of the password locations
    // if they match the key values, the CSM will unlock     
    temp = *PWL0;
    temp = *PWL1;
    temp = *PWL2;
    temp = *PWL3;
    temp = *PWL4;
    temp = *PWL5;
    temp = *PWL6;
    temp = *PWL7;
 
    return(  ((*CSMSCR & 0x0001) == 0) ? 1:0 );
}

//---------------------------------------------------------------------------
// Configure the minimal set of pins to access populated eZdsp connectors.
// This minimal set is configured for loopback testing of SCI/CAN modules
// in the factory.
// 
// SCIB    - GPIO9,11
// CANB    - GPIO9,10
// SCIA    - GPIO28,29
// CANB    - GPIO30,31
// I2C     - GPIO32,33
// LED     - GPIO34
// 
// Other GPIO go to expansion header and can be configured as required
// by user.
//
// Other assumptions for factory test:
// SW2 1-4 ON to select on-board drivers through QS mux
// SW1 4 ON, enable I2C writes
// SW1 5 ON, enable I2C 5K pullups
// SW1 6 OFF, I2C located at addres 0b00
// 
void InitGpio()
{
	EALLOW;	
	
	// Enable SCI-B on GPIO9, GPIO11
	GpioCtrlRegs.GPAQSEL1.bit.GPIO9  = 3;  // asynch input
	GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3;  // asynch input
	GpioCtrlRegs.GPAPUD.bit.GPIO9    = 0;  // Enable pullup on GPIO9  
	GpioCtrlRegs.GPAPUD.bit.GPIO11   = 0;  // Enable pullup on GPIO11             
	GpioCtrlRegs.GPAMUX1.bit.GPIO9   = 2;  // GPIO9 = SCITXDB
	GpioCtrlRegs.GPAMUX1.bit.GPIO11  = 2;  // GPIO11 = SCIRXDB
	
	// Enable CAN-B on GPIO8 - GPIO10   
	GpioCtrlRegs.GPAMUX1.bit.GPIO8  = 2;    // Configure GPIO8 for CANTXB operation
	GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2;	// Configure GPIO10 for CANRXB operation
	GpioCtrlRegs.GPAPUD.bit.GPIO8   = 0;	// Enable internal pull-up for GPIO8
	GpioCtrlRegs.GPAPUD.bit.GPIO10  = 0;	// Enable internal pull-up for GPIO10
	
	// Enable SCI-A on GPIO28 - GPIO29
	GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;  // asynch input
	GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;  // asynch input
	GpioCtrlRegs.GPAPUD.bit.GPIO28   = 0;  // Enable pullup on GPIO28 
	GpioCtrlRegs.GPAPUD.bit.GPIO29   = 0;  // Enable pullup on GPIO29              
	GpioCtrlRegs.GPAMUX2.bit.GPIO28  = 1;  // GPIO28 = SCIRXDA
	GpioCtrlRegs.GPAMUX2.bit.GPIO29  = 1;  // GPIO29 = SCITXDA
    
	// Enable CAN-A on GPIO30 - GPIO31 
	GpioCtrlRegs.GPAPUD.bit.GPIO30    = 0;	// Enable internal pull-up for GPIO8
	GpioCtrlRegs.GPAPUD.bit.GPIO31    = 0;	// Enable internal pull-up for GPIO10
	GpioCtrlRegs.GPAQSEL2.bit.GPIO30  = 3;  // asynch input
	GpioCtrlRegs.GPAQSEL2.bit.GPIO31  = 3;  // asynch input
	GpioCtrlRegs.GPAMUX2.bit.GPIO30   = 1;	// Configure GPIO30 for CANTXA operation
	GpioCtrlRegs.GPAMUX2.bit.GPIO31   = 1;	// Configure GPIO31 for CANRXA operation

	
	// Enable I2C-A on GPIO32 - GPIO33
	GpioCtrlRegs.GPBMUX1.bit.GPIO32  = 1; // GPIO32 = SDAA   
	GpioCtrlRegs.GPBMUX1.bit.GPIO33  = 1; // GPIO33 = SCLA
	
	// Make GPIO34 an output
	GpioCtrlRegs.GPBPUD.bit.GPIO34   = 0; // Enable pullup on GPIO34   
	GpioCtrlRegs.GPBMUX1.bit.GPIO34  = 0; // GPIO34 = GPIO34
	GpioCtrlRegs.GPBDIR.bit.GPIO34   = 1; // GPIO34 = output   
	
    EDIS;    	  
}