clkdiv.tan.rpt

EPM240CPLD的原理图

; N/A                                     ; 247.16 MHz ( period = 4.046 ns )                    ; cnt[14] ; cnt[19]   ; clk        ; clk      ; None                        ; None                      ; 3.337 ns                ;
; N/A                                     ; 250.82 MHz ( period = 3.987 ns )                    ; cnt[16] ; cnt[19]   ; clk        ; clk      ; None                        ; None                      ; 3.278 ns                ;
; N/A                                     ; 250.88 MHz ( period = 3.986 ns )                    ; cnt[15] ; cnt[18]   ; clk        ; clk      ; None                        ; None                      ; 3.277 ns                ;
; N/A                                     ; 252.02 MHz ( period = 3.968 ns )                    ; cnt[6]  ; cnt[9]    ; clk        ; clk      ; None                        ; None                      ; 3.259 ns                ;
; N/A                                     ; 253.49 MHz ( period = 3.945 ns )                    ; cnt[8]  ; cnt[9]    ; clk        ; clk      ; None                        ; None                      ; 3.236 ns                ;
; N/A                                     ; 257.33 MHz ( period = 3.886 ns )                    ; cnt[10] ; cnt[14]   ; clk        ; clk      ; None                        ; None                      ; 3.177 ns                ;
; N/A                                     ; 258.80 MHz ( period = 3.864 ns )                    ; cnt[16] ; cnt[18]   ; clk        ; clk      ; None                        ; None                      ; 3.155 ns                ;
; N/A                                     ; 258.87 MHz ( period = 3.863 ns )                    ; cnt[15] ; cnt[17]   ; clk        ; clk      ; None                        ; None                      ; 3.154 ns                ;
; N/A                                     ; 260.08 MHz ( period = 3.845 ns )                    ; cnt[6]  ; cnt[8]    ; clk        ; clk      ; None                        ; None                      ; 3.136 ns                ;
; N/A                                     ; 263.44 MHz ( period = 3.796 ns )                    ; cnt[0]  ; cnt[1]    ; clk        ; clk      ; None                        ; None                      ; 3.087 ns                ;
; N/A                                     ; 264.34 MHz ( period = 3.783 ns )                    ; cnt[17] ; clk_div_r ; clk        ; clk      ; None                        ; None                      ; 3.074 ns                ;
; N/A                                     ; 265.04 MHz ( period = 3.773 ns )                    ; cnt[1]  ; cnt[4]    ; clk        ; clk      ; None                        ; None                      ; 3.064 ns                ;
; N/A                                     ; 265.04 MHz ( period = 3.773 ns )                    ; cnt[11] ; cnt[14]   ; clk        ; clk      ; None                        ; None                      ; 3.064 ns                ;
; N/A                                     ; 265.75 MHz ( period = 3.763 ns )                    ; cnt[10] ; cnt[13]   ; clk        ; clk      ; None                        ; None                      ; 3.054 ns                ;
; N/A                                     ; 267.31 MHz ( period = 3.741 ns )                    ; cnt[16] ; cnt[17]   ; clk        ; clk      ; None                        ; None                      ; 3.032 ns                ;
; N/A                                     ; 267.38 MHz ( period = 3.740 ns )                    ; cnt[15] ; cnt[16]   ; clk        ; clk      ; None                        ; None                      ; 3.031 ns                ;
; N/A                                     ; 268.02 MHz ( period = 3.731 ns )                    ; cnt[13] ; cnt[14]   ; clk        ; clk      ; None                        ; None                      ; 3.022 ns                ;
; N/A                                     ; 268.02 MHz ( period = 3.731 ns )                    ; cnt[18] ; cnt[19]   ; clk        ; clk      ; None                        ; None                      ; 3.022 ns                ;
; N/A                                     ; 268.67 MHz ( period = 3.722 ns )                    ; cnt[6]  ; cnt[7]    ; clk        ; clk      ; None                        ; None                      ; 3.013 ns                ;
; N/A                                     ; 273.97 MHz ( period = 3.650 ns )                    ; cnt[1]  ; cnt[3]    ; clk        ; clk      ; None                        ; None                      ; 2.941 ns                ;
; N/A                                     ; 273.97 MHz ( period = 3.650 ns )                    ; cnt[2]  ; cnt[4]    ; clk        ; clk      ; None                        ; None                      ; 2.941 ns                ;
; N/A                                     ; 273.97 MHz ( period = 3.650 ns )                    ; cnt[11] ; cnt[13]   ; clk        ; clk      ; None                        ; None                      ; 2.941 ns                ;
; N/A                                     ; 273.97 MHz ( period = 3.650 ns )                    ; cnt[12] ; cnt[14]   ; clk        ; clk      ; None                        ; None                      ; 2.941 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+-----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To      ; From Clock ;
+-------+--------------+------------+-----------+---------+------------+
; N/A   ; None         ; 7.973 ns   ; clk_div_r ; clk_div ; clk        ;
+-------+--------------+------------+-----------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 15:56:41 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clkdiv -c clkdiv
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 154.23 MHz between source register "cnt[8]" and destination register "clk_div_r" (period= 6.484 ns)
    Info: + Longest register to register delay is 5.775 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N8; Fanout = 4; REG Node = 'cnt[8]'
        Info: 2: + IC(2.094 ns) + CELL(0.740 ns) = 2.834 ns; Loc. = LC_X4_Y2_N4; Fanout = 1; COMB Node = 'Equal0~193'
        Info: 3: + IC(0.712 ns) + CELL(0.914 ns) = 4.460 ns; Loc. = LC_X4_Y2_N8; Fanout = 1; COMB Node = 'Equal0~195'
        Info: 4: + IC(0.724 ns) + CELL(0.591 ns) = 5.775 ns; Loc. = LC_X4_Y2_N0; Fanout = 2; REG Node = 'clk_div_r'
        Info: Total cell delay = 2.245 ns ( 38.87 % )
        Info: Total interconnect delay = 3.530 ns ( 61.13 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N0; Fanout = 2; REG Node = 'clk_div_r'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y2_N8; Fanout = 4; REG Node = 'cnt[8]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "clk_div" through register "clk_div_r" is 7.973 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N0; Fanout = 2; REG Node = 'clk_div_r'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.249 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y2_N0; Fanout = 2; REG Node = 'clk_div_r'
        Info: 2: + IC(1.927 ns) + CELL(2.322 ns) = 4.249 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'clk_div'
        Info: Total cell delay = 2.322 ns ( 54.65 % )
        Info: Total interconnect delay = 1.927 ns ( 45.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 15:56:42 2008
    Info: Elapsed time: 00:00:01