led_seg7.tan.rpt

EPM240CPLD的原理图

+-----------------------------------------+-----------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tco                                                                ;
+-------+--------------+------------+--------+----------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To       ; From Clock ;
+-------+--------------+------------+--------+----------+------------+
; N/A   ; None         ; 10.099 ns  ; num[1] ; sm_db[2] ; clk        ;
; N/A   ; None         ; 10.098 ns  ; num[1] ; sm_db[3] ; clk        ;
; N/A   ; None         ; 9.984 ns   ; num[1] ; sm_db[6] ; clk        ;
; N/A   ; None         ; 9.887 ns   ; num[0] ; sm_db[3] ; clk        ;
; N/A   ; None         ; 9.881 ns   ; num[0] ; sm_db[2] ; clk        ;
; N/A   ; None         ; 9.854 ns   ; num[0] ; sm_db[6] ; clk        ;
; N/A   ; None         ; 9.666 ns   ; num[3] ; sm_db[3] ; clk        ;
; N/A   ; None         ; 9.661 ns   ; num[2] ; sm_db[6] ; clk        ;
; N/A   ; None         ; 9.639 ns   ; num[3] ; sm_db[2] ; clk        ;
; N/A   ; None         ; 9.588 ns   ; num[3] ; sm_db[5] ; clk        ;
; N/A   ; None         ; 9.308 ns   ; num[2] ; sm_db[3] ; clk        ;
; N/A   ; None         ; 9.303 ns   ; num[1] ; sm_db[5] ; clk        ;
; N/A   ; None         ; 9.302 ns   ; num[3] ; sm_db[6] ; clk        ;
; N/A   ; None         ; 9.282 ns   ; num[2] ; sm_db[2] ; clk        ;
; N/A   ; None         ; 9.041 ns   ; num[2] ; sm_db[5] ; clk        ;
; N/A   ; None         ; 8.963 ns   ; num[3] ; sm_db[4] ; clk        ;
; N/A   ; None         ; 8.961 ns   ; num[3] ; sm_db[1] ; clk        ;
; N/A   ; None         ; 8.959 ns   ; num[3] ; sm_db[0] ; clk        ;
; N/A   ; None         ; 8.906 ns   ; num[0] ; sm_db[5] ; clk        ;
; N/A   ; None         ; 8.699 ns   ; num[1] ; sm_db[1] ; clk        ;
; N/A   ; None         ; 8.697 ns   ; num[1] ; sm_db[0] ; clk        ;
; N/A   ; None         ; 8.683 ns   ; num[1] ; sm_db[4] ; clk        ;
; N/A   ; None         ; 8.416 ns   ; num[2] ; sm_db[4] ; clk        ;
; N/A   ; None         ; 8.410 ns   ; num[2] ; sm_db[0] ; clk        ;
; N/A   ; None         ; 8.408 ns   ; num[2] ; sm_db[1] ; clk        ;
; N/A   ; None         ; 8.299 ns   ; num[0] ; sm_db[1] ; clk        ;
; N/A   ; None         ; 8.297 ns   ; num[0] ; sm_db[0] ; clk        ;
; N/A   ; None         ; 8.284 ns   ; num[0] ; sm_db[4] ; clk        ;
+-------+--------------+------------+--------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 15:58:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led_seg7 -c led_seg7
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 102.46 MHz between source register "cnt[17]" and destination register "num[3]" (period= 9.76 ns)
    Info: + Longest register to register delay is 9.051 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N9; Fanout = 3; REG Node = 'cnt[17]'
        Info: 2: + IC(2.524 ns) + CELL(0.511 ns) = 3.035 ns; Loc. = LC_X5_Y4_N9; Fanout = 1; COMB Node = 'Equal0~262'
        Info: 3: + IC(1.847 ns) + CELL(0.511 ns) = 5.393 ns; Loc. = LC_X4_Y3_N8; Fanout = 4; COMB Node = 'Equal0~264'
        Info: 4: + IC(1.670 ns) + CELL(0.200 ns) = 7.263 ns; Loc. = LC_X3_Y4_N4; Fanout = 1; COMB Node = 'num[1]~157'
        Info: 5: + IC(1.197 ns) + CELL(0.591 ns) = 9.051 ns; Loc. = LC_X2_Y4_N4; Fanout = 8; REG Node = 'num[3]'
        Info: Total cell delay = 1.813 ns ( 20.03 % )
        Info: Total interconnect delay = 7.238 ns ( 79.97 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 29; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N4; Fanout = 8; REG Node = 'num[3]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 29; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y3_N9; Fanout = 3; REG Node = 'cnt[17]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "sm_db[2]" through register "num[1]" is 10.099 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 29; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N5; Fanout = 10; REG Node = 'num[1]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.375 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N5; Fanout = 10; REG Node = 'num[1]'
        Info: 2: + IC(1.092 ns) + CELL(0.914 ns) = 2.006 ns; Loc. = LC_X2_Y4_N3; Fanout = 1; COMB Node = 'WideOr4~15'
        Info: 3: + IC(2.047 ns) + CELL(2.322 ns) = 6.375 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'sm_db[2]'
        Info: Total cell delay = 3.236 ns ( 50.76 % )
        Info: Total interconnect delay = 3.139 ns ( 49.24 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 15:58:14 2008
    Info: Elapsed time: 00:00:01