led_seg7.map.summary

来自「EPM240CPLD的原理图」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Tue Dec 30 15:58:01 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : led_seg7
Top-level Entity Name : led_seg7
Family : MAX II
Total logic elements : 45
Total pins : 11
Total virtual pins : 0
UFM blocks : 0