led_seg7.fit.rpt

EPM240CPLD的原理图

; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff      ;
; Mid Wire Use - Fit Attempt 1                                                   ; 8       ;
; Mid Slack - Fit Attempt 1                                                      ; -11265  ;
; Internal Atom Count - Fit Attempt 1                                            ; 45      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 45      ;
; LAB Count - Fit Attempt 1                                                      ; 8       ;
; Outputs per Lab - Fit Attempt 1                                                ; 3.750   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 3.000   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.000   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:8     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:8     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:8     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:8     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:4;1:4 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:4;1:4 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:8     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:8     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:8     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:4;2:4 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:4;1:4 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:8     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:4;1:4 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:8     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:8     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:5;1:3 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:8     ;
; LEs in Chains - Fit Attempt 1                                                  ; 24      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 24      ;
; LABs with Chains - Fit Attempt 1                                               ; 3       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
+--------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+------------------------------------+--------+
; Name                               ; Value  ;
+------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff     ;
; Early Wire Use - Fit Attempt 1     ; 1      ;
; Early Slack - Fit Attempt 1        ; -13585 ;
; Auto Fit Point 3 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff     ;
; Mid Wire Use - Fit Attempt 1       ; 3      ;
; Mid Slack - Fit Attempt 1          ; -11108 ;
; Late Wire Use - Fit Attempt 1      ; 3      ;
; Late Slack - Fit Attempt 1         ; -11108 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000  ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Time - Fit Attempt 1               ; 0      ;
+------------------------------------+--------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -9212 ;
; Early Wire Use - Fit Attempt 1      ; 2     ;
; Peak Regional Wire - Fit Attempt 1  ; 2     ;
; Mid Slack - Fit Attempt 1           ; -9484 ;
; Late Slack - Fit Attempt 1          ; -9484 ;
; Late Wire Use - Fit Attempt 1       ; 3     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.032 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 15:58:02 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led_seg7 -c led_seg7
Info: Selected device EPM240T100C5 for design "led_seg7"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted signal "rst_n" to use Global clock
Info: Pin "rst_n" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 10.150 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y3; Fanout = 4; REG Node = 'cnt[11]'
    Info: 2: + IC(2.250 ns) + CELL(0.200 ns) = 2.450 ns; Loc. = LAB_X4_Y4; Fanout = 1; COMB Node = 'Equal0~259'
    Info: 3: + IC(1.763 ns) + CELL(0.511 ns) = 4.724 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'Equal0~261'
    Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.904 ns; Loc. = LAB_X4_Y3; Fanout = 4; COMB Node = 'Equal0~264'
    Info: 5: + IC(1.534 ns) + CELL(0.740 ns) = 8.178 ns; Loc. = LAB_X3_Y4; Fanout = 1; COMB Node = 'num[1]~157'
    Info: 6: + IC(1.381 ns) + CELL(0.591 ns) = 10.150 ns; Loc. = LAB_X2_Y4; Fanout = 8; REG Node = 'num[3]'
    Info: Total cell delay = 2.956 ns ( 29.12 % )
    Info: Total interconnect delay = 7.194 ns ( 70.88 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin sm_cs1_n has GND driving its datain port
    Info: Pin sm_cs2_n has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 157 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 15:58:04 2008
    Info: Elapsed time: 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Documents and Settings/admin/桌面/1230/EPM资料/实验例程以及说明文档/4、数码管显示/verilogled7/led_seg7.fit.smsg.