led_seg7.map.rpt

EPM240CPLD的原理图

; led_seg7.v                       ; yes             ; User Verilog HDL File  ; C:/Documents and Settings/admin/桌面/1230/EPM资料/实验例程以及说明文档/4、数码管显示/verilogled7/led_seg7.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 45    ;
;     -- Combinational with no register       ; 16    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 29    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 17    ;
;     -- 3 input functions                    ; 1     ;
;     -- 2 input functions                    ; 26    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 22    ;
;     -- arithmetic mode                      ; 23    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 29    ;
;                                             ;       ;
; Total registers                             ; 29    ;
; Total logic cells in carry chains           ; 24    ;
; I/O pins                                    ; 11    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 29    ;
; Total fan-out                               ; 189   ;
; Average fan-out                             ; 3.38  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |led_seg7                  ; 45 (45)     ; 29           ; 0          ; 11   ; 0            ; 16 (16)      ; 0 (0)             ; 29 (29)          ; 24 (24)         ; 0 (0)      ; |led_seg7           ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 29    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |led_seg7 ;
+----------------+---------+-----------------------------------------------+
; Parameter Name ; Value   ; Type                                          ;
+----------------+---------+-----------------------------------------------+
; seg0           ; 0111111 ; Unsigned Binary                               ;
; seg1           ; 0000110 ; Unsigned Binary                               ;
; seg2           ; 1011011 ; Unsigned Binary                               ;
; seg3           ; 1001111 ; Unsigned Binary                               ;
; seg4           ; 1100110 ; Unsigned Binary                               ;
; seg5           ; 1101101 ; Unsigned Binary                               ;
; seg6           ; 1111101 ; Unsigned Binary                               ;
; seg7           ; 0000111 ; Unsigned Binary                               ;
; seg8           ; 1111111 ; Unsigned Binary                               ;
; seg9           ; 1101111 ; Unsigned Binary                               ;
; sega           ; 1110111 ; Unsigned Binary                               ;
; segb           ; 1111100 ; Unsigned Binary                               ;
; segc           ; 0111001 ; Unsigned Binary                               ;
; segd           ; 1011110 ; Unsigned Binary                               ;
; sege           ; 1111001 ; Unsigned Binary                               ;
; segf           ; 1110001 ; Unsigned Binary                               ;
+----------------+---------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 15:57:59 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led_seg7 -c led_seg7
Info: Found 1 design units, including 1 entities, in source file led_seg7.v
    Info: Found entity 1: led_seg7
Info: Elaborating entity "led_seg7" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "sm_cs1_n" stuck at GND
    Warning: Pin "sm_cs2_n" stuck at GND
Info: Implemented 56 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 9 output pins
    Info: Implemented 45 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 126 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 15:58:01 2008
    Info: Elapsed time: 00:00:02