csl_chiphal.h

麦克风阵列的TLS自适应波束形成算法仿真

/******************************************************************************\
*           Copyright (C) 2000 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_chiphal.h
* DATE CREATED.. 08/14/2000 
* LAST MODIFIED. 11/05/2001 DM642 , 6411 remove 6400
*           10/03/2001 - CHIP_6713 - MCASP_SUPPORT - IIC_SUPPORT
*                      - DEVCFG register
*                      - redefinition of CHIP_RSET() / CHIP_RGET()
*                      - new CHIP_CRSET() / CHIP_CRGET() => modification of csl_irq.h
*------------------------------------------------------------------------------
* REGISTERS
*
* CSR    - control/status register
* IFR    - interrupt flag register
* ISR    - interrupt set register
* ICR    - interrupt clear register
* IER    - interrupt enable register
* ISTP   - interrupt service table pointer register
* IRP    - interrupt return pointer
* NRP    - non-maskable interrupt return pointer
* AMR    - addressing mode reister
* IN     - input port register  (1)
* OUT    - output port register  (1)
* FADCR  - floating point adder configuration register  (2)
* FAUCR  - floating point auxiliary control register  (2)
* FMCR   - floating point multiplier configuration register  (2)
* DIER   - DSP interrupt exception register  (3)not complete
* EM     - exception mask register  (3) not complete
* ER     - exception flag register  (3) not complete
* GFPGFR - Galois field polynomial generator function register  (3)
* DEVCFG - Device Configuration register  (4)
* DEVSTAT - Device Status Register (5)
* JTAGID - JTAG ID register (5)
*
* (1) only supported on 6701/6711
* (2) only supported on floating point devices
* (3) only supported on 6414/15/16 devices
* (4) only supported on 6713/DM642/6412 devices
* (5) only supported on DM642/6412 devices
*
\******************************************************************************/
#ifndef _CSL_CHIPHAL_H_
#define _CSL_CHIPHAL_H_

#include <csl_stdinc.h>


/******************************************************************************\
* CHIP identification section
\******************************************************************************/
#ifdef CHIP_BASELINE
  #undef CHIP_BASELINE
  #define CHIP_BASELINE 1
#else
  #define CHIP_BASELINE 0
#endif

#if (CHIP_BASELINE)
  #define CHIP_6201 1
#endif

#ifdef CHIP_6201
  #undef CHIP_6201
  #define CHIP_6201 1
#else
  #define CHIP_6201 0
#endif

#ifdef CHIP_6202
  #undef CHIP_6202
  #define CHIP_6202 1
#else
  #define CHIP_6202 0
#endif

#ifdef CHIP_6203
  #undef CHIP_6203
  #define CHIP_6203 1
#else
  #define CHIP_6203 0
#endif

#ifdef CHIP_6204
  #undef CHIP_6204
  #define CHIP_6204 1
#else
  #define CHIP_6204 0
#endif

#ifdef CHIP_6205
  #undef CHIP_6205
  #define CHIP_6205 1
#else
  #define CHIP_6205 0
#endif

#ifdef CHIP_6211
  #undef CHIP_6211
  #define CHIP_6211 1
#else
  #define CHIP_6211 0
#endif

#ifdef CHIP_6701
  #undef CHIP_6701
  #define CHIP_6701 1
#else
  #define CHIP_6701 0
#endif

#ifdef CHIP_6711
  #undef CHIP_6711
  #define CHIP_6711 1
#else
  #define CHIP_6711 0
#endif

#ifdef CHIP_6712
  #undef CHIP_6712
  #define CHIP_6712 1
#else
  #define CHIP_6712 0
#endif


#ifdef CHIP_6713
  #undef CHIP_6713
  #define CHIP_6713 1
#else
  #define CHIP_6713 0
#endif

#ifdef CHIP_DA610
  #undef CHIP_DA610
  #define CHIP_DA610 1
#else
  #define CHIP_DA610 0
#endif

#ifdef CHIP_DM642
  #undef CHIP_DM642
  #define CHIP_DM642 1
#else
  #define CHIP_DM642 0
#endif

#ifdef CHIP_6412
  #undef CHIP_6412
  #define CHIP_6412 1
#else
  #define CHIP_6412 0
#endif

#ifdef CHIP_6414
  #undef CHIP_6414
  #define CHIP_6414 1
#else
  #define CHIP_6414 0
#endif

#ifdef CHIP_6415
  #undef CHIP_6415
  #define CHIP_6415 1
#else
  #define CHIP_6415 0
#endif

#ifdef CHIP_6416
  #undef CHIP_6416
  #define CHIP_6416 1
#else
  #define CHIP_6416 0
#endif


#define CHIP_OROFALL (\
  CHIP_6201 | \
  CHIP_6202 | \
  CHIP_6203 | \
  CHIP_6204 | \
  CHIP_6205 | \
  CHIP_6211 | \
  CHIP_6701 | \
  CHIP_6711 | \
  CHIP_6712 | \
  CHIP_6713 | \
  CHIP_DA610 | \
  CHIP_DM642 | \
  CHIP_6412 | \
  CHIP_6414 | \
  CHIP_6415 | \
  CHIP_6416   \
)

#if (CHIP_OROFALL==0)
  #error NO CHIP DEFINED (use -dCHIP_XXXX where XXXX is chip number, i.e. 6201)
#endif

#define CHIP_NONE 0

#define CHIP_SUPPORT(c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18) ( \
  ( c0*CHIP_6201)  | \
  ( c1*CHIP_6202)  | \
  ( c2*CHIP_6203)  | \
  ( c3*CHIP_6204)  | \
  ( c4*CHIP_6205)  | \
  ( c5*CHIP_6211)  | \
  ( c6*CHIP_6701)  | \
  ( c7*CHIP_6711)  | \
  ( c8*CHIP_6712)  | \
  ( c9*CHIP_6713)  | \
  ( c10*CHIP_DA610)| \
  ( c11*CHIP_DM642)| \
  ( c12*CHIP_6412) | \
  ( c13*CHIP_6414) | \
  ( c14*CHIP_6415) | \
  ( c15*CHIP_6416) | \
  ( c16*CHIP_NONE) | \
  ( c17*CHIP_NONE) | \
  ( c18*CHIP_NONE)   \
 )

/*--------------------------------------------------------------------------*/
/*                                     6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6      */
/*                                     2 2 2 2 2 2 7 7 7 7 1 4 4 4 4 4      */
/*                                     0 0 0 0 0 1 0 1 1 1 0 2 1 1 1 1      */
/*                                     1 2 3 4 5 1 1 1 2 3     2 4 5 6      */
/*--------------------------------------------------------------------------*/
#define CACHE_SUPPORT     CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0)
#define DMA_SUPPORT       CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0)
#define EDMA_SUPPORT      CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,0,0,0)
#define EMIF_SUPPORT      CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0)
#define EMIFA_SUPPORT     CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0) 
#define EMIFB_SUPPORT     CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0) 
#define GPIO_SUPPORT      CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0) 
#define HPI_SUPPORT       CHIP_SUPPORT(1,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,0,0,0)
#define I2C_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0)
#define IRQ_SUPPORT       CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0)
#define MCASP_SUPPORT     CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0) 
#define MCBSP_SUPPORT     CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0)
#define PLL_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0)
#define TIMER_SUPPORT     CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0)
#define XBUS_SUPPORT      CHIP_SUPPORT(0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
#define PCI_SUPPORT       CHIP_SUPPORT(0,0,0,0,1,0,0,0,0,0,0,1,1,0,1,1,0,0,0)
/*--------------------------------------------------------------------------*/
/*                                     6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6      */
/*                                     2 2 2 2 2 2 7 7 7 7 1 4 4 4 4 4      */
/*                                     0 0 0 0 0 1 0 1 1 1 0 2 1 1 1 1      */
/*                                     1 2 3 4 5 1 1 1 2 3     2 4 5 6      */
/*--------------------------------------------------------------------------*/
#define VP_SUPPORT        CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)
#define VIC_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)
#define DAT_SUPPORT       CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0)
#define PWR_SUPPORT       CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0)
#define UTOP_SUPPORT      CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0)
#define TCP_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0)
#define VCP_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0)
#define EMAC_SUPPORT      CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0)
#define MDIO_SUPPORT      CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0)

#define L2CACHE_SUPPORT   CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,0,0,0)
#define TC_SUPPORT        CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,0,0,0)
#define FPU_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,0)
#define C01_SUPPORT       CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0)
#define C11_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,0,0,0,0,0,0,0,0)
#define C64_SUPPORT       CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0)

#define CACHE_L2_SUPPORT  L2CACHE_SUPPORT 
/*----------------------------------------------------------------------*/


/******************************************************************************\
* module level register/field access macros
\******************************************************************************/

  /* ----------------- */
  /* FIELD MAKE MACROS */
  /* ----------------- */

  #define CHIP_FMK(REG,FIELD,x)\
    _PER_FMK(CHIP,##REG,##FIELD,x)

  #define CHIP_FMKS(REG,FIELD,SYM)\
    _PER_FMKS(CHIP,##REG,##FIELD,##SYM)
 
 
  /* -------------------------------- */
  /* RAW REGISTER/FIELD ACCESS MACROS */
  /* -------------------------------- */

  #define CHIP_CRGET(REG)\
    _PER_CRGET(CHIP,##REG)

  #define CHIP_CRSET(REG,x)\
    _PER_CRSET(CHIP,##REG,x)

  #define CHIP_RGET(REG)\
   _PER_RGET(_CHIP_##REG##_ADDR,CHIP,##REG)

  #define CHIP_RSET(REG,x)\
     _PER_RSET(_CHIP_##REG##_ADDR,CHIP,##REG,x)


  #define CHIP_FGET(REG,FIELD)\
    _CHIP_##REG##_FGET(##FIELD)

  #define CHIP_FSET(REG,FIELD,x)\
    _CHIP_##REG##_FSET(##FIELD,x)

  #define CHIP_FSETS(REG,FIELD,SYM)\
    _CHIP_##REG##_FSETS(##FIELD,##SYM)
 

/******************************************************************************\
* _____________________
* |                   |
* |  C S R            |
* |___________________|
*
* CSR - control/status register
*
* FIELDS (msb -> lsb)
* (r)  CPUID
* (r)  REVID
* (rw) PWRD
* (rc) SAT
* (r)  EN
* (rw) PCC
* (rw) DCC
* (rw) PGIE
* (rw) GIE
*
\******************************************************************************/
  extern far cregister volatile unsigned int CSR;

  #define _CHIP_CSR_CPUID_MASK         0xFF000000u
  #define _CHIP_CSR_CPUID_SHIFT        0x00000018u
  #define  CHIP_CSR_CPUID_DEFAULT      0x00000000u
  #define  CHIP_CSR_CPUID_OF(x)        _VALUEOF(x)
  #define  CHIP_CSR_CPUID_C62X         0x00000000u
  #define  CHIP_CSR_CPUID_C67X         0x00000002u
  #define  CHIP_CSR_CPUID_C64X         0x00000004u

  #define _CHIP_CSR_REVID_MASK         0x00FF0000u
  #define _CHIP_CSR_REVID_SHIFT        0x00000010u
  #define  CHIP_CSR_REVID_DEFAULT      0x00000000u
  #define  CHIP_CSR_REVID_OF(x)        _VALUEOF(x)
  #define  CHIP_CSR_REVID_620120       0x00000001u
  #define  CHIP_CSR_REVID_620121       0x00000001u
  #define  CHIP_CSR_REVID_620130       0x00000002u
  #define  CHIP_CSR_REVID_670100       0x00000201u
  #define  CHIP_CSR_REVID_670110       0x00000202u
  #define  CHIP_CSR_REVID_621110       0x00000002u
  #define  CHIP_CSR_REVID_640010       0x00000801u

  #define _CHIP_CSR_PWRD_MASK          0x0000FC00u
  #define _CHIP_CSR_PWRD_SHIFT         0x0000000Au
  #define  CHIP_CSR_PWRD_DEFAULT       0x00000000u
  #define  CHIP_CSR_PWRD_OF(x)         _VALUEOF(x)
  #define  CHIP_CSR_PWRD_NONE          0x00000000u
  #define  CHIP_CSR_PWRD_PD1A          0x00000009u
  #define  CHIP_CSR_PWRD_PD1B          0x00000011u
  #define  CHIP_CSR_PWRD_PD2           0x0000001Au
  #define  CHIP_CSR_PWRD_PD3           0x0000001Cu

  #define _CHIP_CSR_SAT_MASK           0x00000200u
  #define _CHIP_CSR_SAT_SHIFT          0x00000009u
  #define  CHIP_CSR_SAT_DEFAULT        0x00000000u
  #define  CHIP_CSR_SAT_OF(x)          _VALUEOF(x)
  #define  CHIP_CSR_SAT_0              0x00000000u
  #define  CHIP_CSR_SAT_1              0x00000001u

  #define _CHIP_CSR_EN_MASK            0x00000100u
  #define _CHIP_CSR_EN_SHIFT           0x00000008u
  #define  CHIP_CSR_EN_DEFAULT         0x00000000u
  #define  CHIP_CSR_EN_OF(x)           _VALUEOF(x)
  #define  CHIP_CSR_EN_BIG             0x00000000u
  #define  CHIP_CSR_EN_LITTLE          0x00000001u

  #define _CHIP_CSR_PCC_MASK           0x000000E0u
  #define _CHIP_CSR_PCC_SHIFT          0x00000005u
  #define  CHIP_CSR_PCC_DEFAULT        0x00000000u
  #define  CHIP_CSR_PCC_OF(x)          _VALUEOF(x)
  #define  CHIP_CSR_PCC_MAPPED         0x00000000u
  #define  CHIP_CSR_PCC_ENABLE         0x00000002u
  #define  CHIP_CSR_PCC_FREEZE         0x00000003u
  #define  CHIP_CSR_PCC_BYPASS         0x00000004u

  #define _CHIP_CSR_DCC_MASK           0x0000001Cu
  #define _CHIP_CSR_DCC_SHIFT          0x00000002u
  #define  CHIP_CSR_DCC_DEFAULT        0x00000000u