csl_edmahal.h

麦克风阵列的TLS自适应波束形成算法仿真

  #define _EDMA_PQAR1_FSET(FIELD,field)\
    _PER_FSET(_EDMA_PQAR1_ADDR,EDMA,PQAR1,FIELD,field)

  #define _EDMA_PQAR1_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_PQAR1_ADDR,EDMA,PQAR1,FIELD,##SYM)
#endif

/******************************************************************************\
* _____________________
* |                   |
* |  P Q A R 2        |
* |___________________|
*
* PQAR2 - priority queue allocation register 2
*
* FIELDS (msb -> lsb)
* (r) PQA
*
\******************************************************************************/
  #if (C64_SUPPORT)
  #define _EDMA_PQAR2_ADDR              0x01A0FFC8u

  #define  EDMA_PQAR2                   EDMA_REG(PQAR2)

  #define _EDMA_PQAR2_PQA_MASK           0x00000007u
  #define _EDMA_PQAR2_PQA_SHIFT          0x00000000u
  #define  EDMA_PQAR2_PQA_DEFAULT        0x00000002u
  #define  EDMA_PQAR2_PQA_OF(x)          _VALUEOF(x)

  #define  EDMA_PQAR2_OF(x)             _VALUEOF(x)

  #define EDMA_PQAR2_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,PQAR2,PQA)\
  )

  #define EDMA_PQAR2_RMK(pqa) (Uint32)(\
     _PER_FMK(EDMA,PQAR2,PQA,pqa)\
  )

  #define _EDMA_PQAR2_FGET(FIELD)\
    _PER_FGET(_EDMA_PQAR2_ADDR,EDMA,PQAR2,FIELD)

  #define _EDMA_PQAR2_FSET(FIELD,field)\
    _PER_FSET(_EDMA_PQAR2_ADDR,EDMA,PQAR2,FIELD,field)

  #define _EDMA_PQAR2_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_PQAR2_ADDR,EDMA,PQAR2,FIELD,##SYM)
#endif

/******************************************************************************\
* _____________________
* |                   |
* |  P Q A R 3        |
* |___________________|
*
* PQAR3 - priority queue allocation register 3
*
* FIELDS (msb -> lsb)
* (r) PQA
*
\******************************************************************************/
  #if (C64_SUPPORT)
  #define _EDMA_PQAR3_ADDR              0x01A0FFCCu

  #define  EDMA_PQAR3                   EDMA_REG(PQAR3)

  #define _EDMA_PQAR3_PQA_MASK           0x00000007u
  #define _EDMA_PQAR3_PQA_SHIFT          0x00000000u
  #define  EDMA_PQAR3_PQA_DEFAULT        0x00000006u
  #define  EDMA_PQAR3_PQA_OF(x)          _VALUEOF(x)

  #define  EDMA_PQAR3_OF(x)             _VALUEOF(x)

  #define EDMA_PQAR3_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,PQAR3,PQA)\
  )

  #define EDMA_PQAR3_RMK(pqa) (Uint32)(\
     _PER_FMK(EDMA,PQAR3,PQA,pqa)\
  )

  #define _EDMA_PQAR3_FGET(FIELD)\
    _PER_FGET(_EDMA_PQAR3_ADDR,EDMA,PQAR3,FIELD)

  #define _EDMA_PQAR3_FSET(FIELD,field)\
    _PER_FSET(_EDMA_PQAR3_ADDR,EDMA,PQAR3,FIELD,field)

  #define _EDMA_PQAR3_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_PQAR3_ADDR,EDMA,PQAR3,FIELD,##SYM)
#endif

/******************************************************************************\
* _____________________
* |                   |
* |  C I P R          |
* |___________________|
*
* CIPR  - channel interrupt pending register
*
* FIELDS (msb -> lsb)
* (rw) CIP
*
\******************************************************************************/
 #define _EDMA_CIPR_ADDR              0x01A0FFE4u

  #define  EDMA_CIPR                   EDMA_REG(CIPR)
  
#if (C64_SUPPORT)
  #define _EDMA_CIPR_CIP_MASK          0xFFFFFFFFu
  #define _EDMA_CIPR_CIP_SHIFT         0x00000000u
  #define  EDMA_CIPR_CIP_DEFAULT       0x00000000u
  #define  EDMA_CIPR_CIP_OF(x)         _VALUEOF(x)
#else
  #define _EDMA_CIPR_CIP_MASK          0x0000FFFFu
  #define _EDMA_CIPR_CIP_SHIFT         0x00000000u
  #define  EDMA_CIPR_CIP_DEFAULT       0x00000000u
  #define  EDMA_CIPR_CIP_OF(x)         _VALUEOF(x)
#endif

  #define  EDMA_CIPR_OF(x)             _VALUEOF(x)

  #define EDMA_CIPR_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CIPR,CIP)\
  )

  #define EDMA_CIPR_RMK(cip) (Uint32)(\
     _PER_FMK(EDMA,CIPR,CIP,cip)\
  )
   
  #define _EDMA_CIPR_FGET(FIELD)\
    _PER_FGET(_EDMA_CIPR_ADDR,EDMA,CIPR,##FIELD)

  #define _EDMA_CIPR_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CIPR_ADDR,EDMA,CIPR,##FIELD,field)

  #define _EDMA_CIPR_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CIPR_ADDR,EDMA,CIPR,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  C I P R L        |
* |___________________|
*
* CIPRL - channel interrupt pending register, low half (1)
*
* (1) - C64x devices only
*
* FIELDS (msb -> lsb)
* (rw) CIP
*
\******************************************************************************/
#if (C64_SUPPORT)
  #define _EDMA_CIPRL_ADDR              0x01A0FFE4u

  #define  EDMA_CIPRL                   EDMA_REG(CIPRL)

  #define _EDMA_CIPRL_CIP_MASK          0xFFFFFFFFu
  #define _EDMA_CIPRL_CIP_SHIFT         0x00000000u
  #define  EDMA_CIPRL_CIP_DEFAULT       0x00000000u
  #define  EDMA_CIPRL_CIP_OF(x)         _VALUEOF(x)

  #define  EDMA_CIPRL_OF(x)             _VALUEOF(x)

  #define EDMA_CIPRL_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CIPRL,CIP)\
  )

  #define EDMA_CIPRL_RMK(cip) (Uint32)(\
     _PER_FMK(EDMA,CIPRL,CIP,cip)\
  )
   
  #define _EDMA_CIPRL_FGET(FIELD)\
    _PER_FGET(_EDMA_CIPRL_ADDR,EDMA,CIPRL,##FIELD)

  #define _EDMA_CIPRL_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CIPRL_ADDR,EDMA,CIPRL,##FIELD,field)

  #define _EDMA_CIPRL_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CIPRL_ADDR,EDMA,CIPRL,##FIELD,##SYM)
#endif


/******************************************************************************\
* _____________________
* |                   |
* |  C I P R H        |
* |___________________|
*
* CIPRH - channel interrupt pending register, high half (1)
*
* (1) - C64x devices only
*
* FIELDS (msb -> lsb)
* (rw) CIP
*
\******************************************************************************/
#if (C64_SUPPORT)
  #define _EDMA_CIPRH_ADDR              0x01A0FFA4u

  #define  EDMA_CIPRH                   EDMA_REG(CIPRH)

  #define _EDMA_CIPRH_CIP_MASK          0xFFFFFFFFu
  #define _EDMA_CIPRH_CIP_SHIFT         0x00000000u
  #define  EDMA_CIPRH_CIP_DEFAULT       0x00000000u
  #define  EDMA_CIPRH_CIP_OF(x)         _VALUEOF(x)

  #define  EDMA_CIPRH_OF(x)             _VALUEOF(x)

  #define EDMA_CIPRH_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CIPRH,CIP)\
  )

  #define EDMA_CIPRH_RMK(cip) (Uint32)(\
     _PER_FMK(EDMA,CIPRH,CIP,cip)\
  )
   
  #define _EDMA_CIPRH_FGET(FIELD)\
    _PER_FGET(_EDMA_CIPRH_ADDR,EDMA,CIPRH,##FIELD)

  #define _EDMA_CIPRH_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CIPRH_ADDR,EDMA,CIPRH,##FIELD,field)

  #define _EDMA_CIPRH_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CIPRH_ADDR,EDMA,CIPRH,##FIELD,##SYM)
#endif


/******************************************************************************\
* _____________________
* |                   |
* |  C I E R          |
* |___________________|
*
* CIER - channel interrupt enable register
*
* FIELDS (msb -> lsb)
* (rw) CIE
*
\******************************************************************************/
  #define _EDMA_CIER_ADDR              0x01A0FFE8u

  #define  EDMA_CIER                   EDMA_REG(CIER)

#if (C64_SUPPORT)
  #define _EDMA_CIER_CIE_MASK          0xFFFFFFFFu
  #define _EDMA_CIER_CIE_SHIFT         0x00000000u
  #define  EDMA_CIER_CIE_DEFAULT       0x00000000u
  #define  EDMA_CIER_CIE_OF(x)         _VALUEOF(x)
#else
  #define _EDMA_CIER_CIE_MASK          0x0000FFFFu
  #define _EDMA_CIER_CIE_SHIFT         0x00000000u
  #define  EDMA_CIER_CIE_DEFAULT       0x00000000u
  #define  EDMA_CIER_CIE_OF(x)         _VALUEOF(x)
#endif

  #define  EDMA_CIER_OF(x)             _VALUEOF(x)

  #define EDMA_CIER_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CIER,CIE)\
  )

  #define EDMA_CIER_RMK(cie) (Uint32)(\
     _PER_FMK(EDMA,CIER,CIE,cie)\
  )
   
  #define _EDMA_CIER_FGET(FIELD)\
    _PER_FGET(_EDMA_CIER_ADDR,EDMA,CIER,##FIELD)

  #define _EDMA_CIER_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CIER_ADDR,EDMA,CIER,##FIELD,field)

  #define _EDMA_CIER_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CIER_ADDR,EDMA,CIER,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  C I E R L        |
* |___________________|
*
* CIERL - channel interrupt enable register, low half (1)
*
* (1) - C64x devices only
*
* FIELDS (msb -> lsb)
* (rw) CIE
*
\******************************************************************************/
#if (C64_SUPPORT)
  #define _EDMA_CIERL_ADDR              0x01A0FFE8u

  #define  EDMA_CIERL                   EDMA_REG(CIERL)

  #define _EDMA_CIERL_CIE_MASK          0xFFFFFFFFu
  #define _EDMA_CIERL_CIE_SHIFT         0x00000000u
  #define  EDMA_CIERL_CIE_DEFAULT       0x00000000u
  #define  EDMA_CIERL_CIE_OF(x)         _VALUEOF(x)

  #define  EDMA_CIERL_OF(x)             _VALUEOF(x)

  #define EDMA_CIERL_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CIERL,CIE)\
  )

  #define EDMA_CIERL_RMK(cie) (Uint32)(\
     _PER_FMK(EDMA,CIERL,CIE,cie)\
  )
   
  #define _EDMA_CIERL_FGET(FIELD)\
    _PER_FGET(_EDMA_CIERL_ADDR,EDMA,CIERL,##FIELD)

  #define _EDMA_CIERL_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CIERL_ADDR,EDMA,CIERL,##FIELD,field)

  #define _EDMA_CIERL_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CIERL_ADDR,EDMA,CIERL,##FIELD,##SYM)
#endif


/******************************************************************************\
* _____________________
* |                   |
* |  C I E R H        |
* |___________________|
*
* CIERL - channel interrupt enable register, high half (1)
*
* (1) - C64x devices only
*
* FIELDS (msb -> lsb)
* (rw) CIE
*
\******************************************************************************/
#if (C64_SUPPORT)
  #define _EDMA_CIERH_ADDR              0x01A0FFA8u

  #define  EDMA_CIERH                   EDMA_REG(CIERH)

  #define _EDMA_CIERH_CIE_MASK          0xFFFFFFFFu
  #define _EDMA_CIERH_CIE_SHIFT         0x00000000u
  #define  EDMA_CIERH_CIE_DEFAULT       0x00000000u
  #define  EDMA_CIERH_CIE_OF(x)         _VALUEOF(x)

  #define  EDMA_CIERH_OF(x)             _VALUEOF(x)

  #define EDMA_CIERH_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CIERH,CIE)\
  )

  #define EDMA_CIERH_RMK(cie) (Uint32)(\
     _PER_FMK(EDMA,CIERH,CIE,cie)\
  )
   
  #define _EDMA_CIERH_FGET(FIELD)\
    _PER_FGET(_EDMA_CIERH_ADDR,EDMA,CIERH,##FIELD)

  #define _EDMA_CIERH_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CIERH_ADDR,EDMA,CIERH,##FIELD,field)

  #define _EDMA_CIERH_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CIERH_ADDR,EDMA,CIERH,##FIELD,##SYM)
#endif


/******************************************************************************\
* _____________________
* |                   |
* |  C C E R          |
* |___________________|
*
* CCER - channel chain enable register
*
* FIELDS (msb -> lsb)
* (rw) CCE
*
\******************************************************************************/
  #define _EDMA_CCER_ADDR              0x01A0FFECu

  #define  EDMA_CCER                   EDMA_REG(CCER)

#if (C64_SUPPORT)
  #define _EDMA_CCER_CCE_MASK          0xFFFFFFFFu
  #define _EDMA_CCER_CCE_SHIFT         0x00000000u
  #define  EDMA_CCER_CCE_DEFAULT       0x00000000u
  #define  EDMA_CCER_CCE_OF(x)         _VALUEOF(x)
#else
  #define _EDMA_CCER_CCE_MASK          0x00000F00u
  #define _EDMA_CCER_CCE_SHIFT         0x00000008u
  #define  EDMA_CCER_CCE_DEFAULT       0x00000000u
  #define  EDMA_CCER_CCE_OF(x)         _VALUEOF(x)
#endif

  #define  EDMA_CCER_OF(x)             _VALUEOF(x)

  #define EDMA_CCER_DEFAULT (Uint32)(\
     _PER_FDEFAULT(EDMA,CCER,CCE)\
  )

  #define EDMA_CCER_RMK(cce) (Uint32)(\
     _PER_FMK(EDMA,CCER,CCE,cce)\
  )

  #define _EDMA_CCER_FGET(FIELD)\
    _PER_FGET(_EDMA_CCER_ADDR,EDMA,CCER,##FIELD)

  #define _EDMA_CCER_FSET(FIELD,field)\
    _PER_FSET(_EDMA_CCER_ADDR,EDMA,CCER,##FIELD,field)

  #define _EDMA_CCER_FSETS(FIELD,SYM)\
    _PER_FSETS(_EDMA_CCER_ADDR,EDMA,CCER,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  C C E R L        |
* |___________________|
*
* CCERL - channel chain enable register, low half (1)
*
* (1) - C64x devices only
*
* FIELDS (msb -> lsb)
* (rw) CCE
*
\******************************************************************************/
#if (C64_SUPPORT)
  #define _EDMA_CCERL_ADDR              0x01A0FFECu

  #define  EDMA_CCERL                   EDMA_REG(CCERL)

  #define _EDMA_CCERL_CCE_MASK          0xFFFFFFFFu
  #define _EDMA_CCERL_CCE_SHIFT         0x00000000u
  #define  EDMA_CCERL_CCE_DEFAULT       0x00000000u
  #define  EDMA_CCERL_CCE_OF(x)         _VALUEOF(x)

  #define  EDMA_CCERL_OF(x)             _VALUEOF(x)

  #define EDMA_CCERL_DEFAULT (Uint32)(\