📄 iar7166.h
字号:
IBGAIN_R DEFINE 0x1C
WGAIN_R DEFINE 0x1D
VARGAIN_R DEFINE 0x1E
VAGAIN_R DEFINE 0x1F
WATTOS_R DEFINE 0x20
VAROS_R DEFINE 0x21
IRMSOS_R DEFINE 0x22
VRMSOS_R DEFINE 0x23
WDIV_R DEFINE 0x24
VARDIV_R DEFINE 0x25
VADIV_R DEFINE 0x26
CF1NUM_R DEFINE 0x27
CF1DEN_R DEFINE 0x28
CF2NUM_R DEFINE 0x29
CF2DEN_R DEFINE 0x2A
MODE3_R DEFINE 0x2B
CALMODE_R DEFINE 0x3D
WATTHR_W DEFINE 0x81
RWATTHR_W DEFINE 0x82
LWATTHR_W DEFINE 0x83
VARHR_W DEFINE 0x84
RVARHR_W DEFINE 0x85
LVARHR_W DEFINE 0x86
VAHR_W DEFINE 0x87
RVAHR_W DEFINE 0x88
LVAHR_W DEFINE 0x89
PER_FREQ_W DEFINE 0x8A
MODE1_W DEFINE 0x8B
MODE2_W DEFINE 0x8C
WAVMODE_W DEFINE 0x8D
NLMODE_W DEFINE 0x8E
ACCMODE_W DEFINE 0x8F
PHCAL_W DEFINE 0x90
ZXTOUT_W DEFINE 0x91
LINCYC_W DEFINE 0x92
SAGCYC_W DEFINE 0x93
SAGLVL_W DEFINE 0x94
IPKLVL_W DEFINE 0x95
VPKLVL_W DEFINE 0x96
IPEAK_W DEFINE 0x97
RSTIPEAK_W DEFINE 0x98
VPEAK_W DEFINE 0x99
RSTVPEAK_W DEFINE 0x9A
GAIN_W DEFINE 0x9B
IBGAIN_W DEFINE 0x9C
WGAIN_W DEFINE 0x9D
VARGAIN_W DEFINE 0x9E
VAGAIN_W DEFINE 0x9F
WATTOS_W DEFINE 0xA0
VAROS_W DEFINE 0xA1
IRMSOS_W DEFINE 0xA2
VRMSOS_W DEFINE 0xA3
WDIV_W DEFINE 0xA4
VARDIV_W DEFINE 0xA5
VADIV_W DEFINE 0xA6
CF1NUM_W DEFINE 0xA7
CF1DEN_W DEFINE 0xA8
CF2NUM_W DEFINE 0xA9
CF2DEN_W DEFINE 0xAA
MODE3_W DEFINE 0xAB
CALMODE_W DEFINE 0xBD
//***************************************************
//***** METER NON-BIT ADDRESSABLE BIT DEFINITIONS *****
//***************************************************
//MODE1
DISHPF DEFINE 0x01
DISCF1 DEFINE 0x02
DISCF2 DEFINE 0x04
PWRDN DEFINE 0x08
SWAPBITS DEFINE 0x10
INTE DEFINE 0x20
DISZXLPF DEFINE 0x40
SWRST DEFINE 0x80
//MODE2
FREQSEL DEFINE 0x02
ZXRMS DEFINE 0x04
VARMSCFCON DEFINE 0x08
CF1SEL0 DEFINE 0x10
CF1SEL1 DEFINE 0x20
CF2SEL0 DEFINE 0x40
CF2SEL1 DEFINE 0x80
//MODE3
ZX1 DEFINE 0x01
ZX2 DEFINE 0x02
CF1WATT DEFINE 0x00
CF2VAR DEFINE 0x40
//WAVMODE
DTRT0 DEFINE 0x01
DTRT1 DEFINE 0x02
WAV1SEL0 DEFINE 0x04
WAV1SEL1 DEFINE 0x08
WAV1SEL2 DEFINE 0x10
WAV2SEL0 DEFINE 0x20
WAV2SEL1 DEFINE 0x40
WAV2SEL2 DEFINE 0x80
//NLMODE
APNOLOAD0 DEFINE 0x01
APNOLOAD1 DEFINE 0x02
VARNOLOAD0 DEFINE 0x04
VARNOLOAD1 DEFINE 0x08
VANOLOAD0 DEFINE 0x10
VANOLOAD1 DEFINE 0x20
IRMSNOLOAD DEFINE 0x40
//ACCMODE
ABSAM DEFINE 0x01
POAM DEFINE 0x02
SAVARM DEFINE 0x04
ABSVARM DEFINE 0x08
APSIGN_INT DEFINE 0x10
VARSIGN_INT DEFINE 0x20
FAULTSIGN_INT DEFINE 0x40
ICHANNEL DEFINE 0x80
//GAIN
PGA1_0 DEFINE 0x01
PGA1_1 DEFINE 0x02
PGA1_2 DEFINE 0x04
PGA2_0 DEFINE 0x20
PGA2_1 DEFINE 0x40
PGA2_2 DEFINE 0x80
//CALMODE
I_CH_SHORT DEFINE 0x04
V_CH_SHORT DEFINE 0x08
SEL_I_CH0 DEFINE 0x10
SEL_I_CH1 DEFINE 0x20
//MIRQSTL/MIRQENL
APNOLOAD DEFINE 0x01
RNOLOAD DEFINE 0x02
VANOLOAD DEFINE 0x04
APSIGN DEFINE 0x08
VARSIGN DEFINE 0x10
FAULTSIGN DEFINE 0x20
ADEIRQFLAG DEFINE 0x80
//MIRQSTM/MIRQENM
AEHF DEFINE 0x01
REHF DEFINE 0x02
VAEHF DEFINE 0x04
AEOF DEFINE 0x08
REOF DEFINE 0x10
VAEOF DEFINE 0x20
CF1INT DEFINE 0x40
CF2INT DEFINE 0x80
//MIRQSTH/MIRQENH
ZX DEFINE 0x01
ZXTO DEFINE 0x02
CYCEND DEFINE 0x04
PKV DEFINE 0x08
PKI DEFINE 0x10
WFSM DEFINE 0x20
END_RESET DEFINE 0x80
//***************************************************
//***** LCD NON-BIT ADDRESSABLE BIT DEFINITIONS *****
//***************************************************
//LCDCON
LMUX0 DEFINE 0x01
LMUX1 DEFINE 0x02
BIAS DEFINE 0x04
CLKSEL DEFINE 0x08
LCDPSM2 DEFINE 0x10
BLINKEN DEFINE 0x20
LCDRST DEFINE 0x40
LCDEN DEFINE 0x80
MUX4_BIAS3 DEFINE 0x07
//LCDCONX
BIASLVL0 DEFINE 0x01
BIASLVL1 DEFINE 0x02
BIASLVL2 DEFINE 0x04
BIASLVL3 DEFINE 0x08
BIASLVL4 DEFINE 0x10
BIASLVL5 DEFINE 0x20
EXTRES DEFINE 0x40
//LCDCONY
REFRESH DEFINE 0x01
UPDATEOVER DEFINE 0x02
SCREENSEL0 DEFINE 0x04
SCREENSEL1 DEFINE 0x08
INVLVL DEFINE 0x40
AUTOSCROLL DEFINE 0x80
//LCDCLK
FD0 DEFINE 0x01
FD1 DEFINE 0x02
FD2 DEFINE 0x04
FD3 DEFINE 0x08
BLKFREQ0 DEFINE 0x10
BLKFREQ1 DEFINE 0x20
BLKMOD0 DEFINE 0x40
BLKMOD1 DEFINE 0x80
//LCDSEGE
FDELAY0 DEFINE 0x01
FDELAY1 DEFINE 0x02
SEG20EN DEFINE 0x04
SEG21EN DEFINE 0x08
SEG22EN DEFINE 0x10
SEG23EN DEFINE 0x20
SEG24EN DEFINE 0x40
SEG25EN DEFINE 0x80
//LCDPTR
ADDRESS0 DEFINE 0x01
ADDRESS1 DEFINE 0x02
ADDRESS2 DEFINE 0x04
ADDRESS3 DEFINE 0x08
ADDRESS4 DEFINE 0x10
ADDRESS5 DEFINE 0x20
WR DEFINE 0x80
//LCDDAT
LCDDATA0 DEFINE 0x01
LCDDATA1 DEFINE 0x02
LCDDATA2 DEFINE 0x04
LCDDATA3 DEFINE 0x08
LCDDATA4 DEFINE 0x10
LCDDATA5 DEFINE 0x20
LCDDATA6 DEFINE 0x40
LCDDATA7 DEFINE 0x80
//LCDSEGE2
SEG16EN DEFINE 0x01
SEG17EN DEFINE 0x02
SEG18EN DEFINE 0x04
SEG19EN DEFINE 0x08
//*****************************************************
//POWER MANAGEMENT NON-BIT ADDRESSABLE BIT DEFINITIONS
//*****************************************************
//PERIPH
RXPROG0 DEFINE 0x01
RXPROG1 DEFINE 0x02
EXTREFEN DEFINE 0x04
REF_BAT_EN DEFINE 0x08
PLL_FLT DEFINE 0x10
VDD_OK DEFINE 0x20
VSWSOURCE DEFINE 0x40
RXFLAG DEFINE 0x80
//BATPR
BATPRG0 DEFINE 0x01
BATPRG1 DEFINE 0x02
//INTPR
INT0PRG DEFINE 0x01
INT1PRG0 DEFINE 0x02
INT1PRG1 DEFINE 0x04
INT1PRG2 DEFINE 0x08
RTCCAL DEFINE 0x80
INT1GPIO DEFINE 0x00
INT1BCTRL DEFINE 0x02
INT1NOWAKE DEFINE 0x04
INT1WAKE DEFINE 0x0C
//IPSME
EVDCIN DEFINE 0x01
EBSO DEFINE 0x02
EBAT DEFINE 0x04
EVSW DEFINE 0x08
ESAG DEFINE 0x20
ADEIAUTCLR DEFINE 0x40
EPSR DEFINE 0x80
//KYREG
KYREGKEY DEFINE 0xA7
//POWCON
//(NOTE: write 0xA7 to KYREG before writing this register)
CD0 DEFINE 0x01
CD1 DEFINE 0x02
CD2 DEFINE 0x04
COREOFF DEFINE 0x10
;***************************************************
;***** MISC NON-BIT ADDRESSABLE BIT DEFINITIONS *****
;***************************************************
//IEIP2
ESI DEFINE 0x01
EPSM DEFINE 0x02
ETI DEFINE 0x04
EADE DEFINE 0x08
PSI DEFINE 0x10
ES2 DEFINE 0x20
PTI DEFINE 0x40
PS2 DEFINE 0x80
//CFG
XREN0 DEFINE 0x01
XREN1 DEFINE 0x02
MOD38EN DEFINE 0x10
SCPS DEFINE 0x20
EXTEN DEFINE 0x40
//STRBPER
TEMP_PERIOD0 DEFINE 0x01
TEMP_PERIOD1 DEFINE 0x02
BATT_PERIOD0 DEFINE 0x04
BATT_PERIOD1 DEFINE 0x08
VSW_PERIOD0 DEFINE 0x10
VSW_PERIOD1 DEFINE 0x20
//DIFFPROG
VSW_DIFF0 DEFINE 0x01
VSW_DIFF1 DEFINE 0x02
VSW_DIFF2 DEFINE 0x04
TEMP_DIFF0 DEFINE 0x08
TEMP_DIFF1 DEFINE 0x10
TEMP_DIFF2 DEFINE 0x20
//SPIMOD2
TIMODE DEFINE 0x01
SPILSBF DEFINE 0x02
SPICPHA DEFINE 0x04
SPICPOL DEFINE 0x08
SPIMS_b DEFINE 0x10
SPIODO DEFINE 0x20
SPIEN DEFINE 0x40
SPICONT DEFINE 0x80
//SPISTAT
SPITxBF DEFINE 0x01
SPITxIRQ DEFINE 0x02
SPITxUF DEFINE 0x04
SPIRxBF DEFINE 0x08
SPIRxIRQ DEFINE 0x10
SPIRxOF DEFINE 0x20
MMERR DEFINE 0x40
SPIBUSY DEFINE 0x80
//I2CSTAT
I2CTxWR_ERR DEFINE 0x01
I2CACC_ERR DEFINE 0x02
I2CFIFOSTAT0 DEFINE 0x04
I2CFIFOSTAT1 DEFINE 0x08
I2CTxIRQ DEFINE 0x10
I2CRxIRQ DEFINE 0x20
I2CNOACK DEFINE 0x40
I2CBUSY DEFINE 0x80
//PINMAP0
PINMAP0_0 DEFINE 0x01
PINMAP0_1 DEFINE 0x02
PINMAP0_2 DEFINE 0x04
PINMAP0_3 DEFINE 0x08
PINMAP0_4 DEFINE 0x10
PINMAP0_5 DEFINE 0x20
PINMAP0_6 DEFINE 0x40
PINMAP0_7 DEFINE 0x80
//PINMAP1
PINMAP1_0 DEFINE 0x01
PINMAP1_1 DEFINE 0x02
PINMAP1_2 DEFINE 0x04
PINMAP1_3 DEFINE 0x08
PINMAP1_4 DEFINE 0x10
PINMAP1_5 DEFINE 0x20
PINMAP1_6 DEFINE 0x40
PINMAP1_7 DEFINE 0x80
//PINMAP2
PINMAP2_0 DEFINE 0x01
PINMAP2_1 DEFINE 0x02
PINMAP2_2 DEFINE 0x04
PINMAP2_3 DEFINE 0x08
PINMAP2_5 DEFINE 0x20
//TIMECON
ITEN DEFINE 0x02
ITFLAG DEFINE 0x04
SIT DEFINE 0x08
ITS0 DEFINE 0x10
ITS1 DEFINE 0x20
ALFLAG DEFINE 0x40
//TIMECON2
ALSEC_EN DEFINE 0x01
ALMIN_EN DEFINE 0x02
ALHR_EN DEFINE 0x04
ALDAY_EN DEFINE 0x08
ALDAT_EN DEFINE 0x10
//DPCON
DPSEL DEFINE 0x01
DP0m0 DEFINE 0x04
DP0m1 DEFINE 0x08
DP1m0 DEFINE 0x10
DP1m1 DEFINE 0x20
DPT DEFINE 0x40
//SBAUDF
SBAUDF_0 DEFINE 0x01
SBAUDF_1 DEFINE 0x04
SBAUDF_2 DEFINE 0x08
SBAUDF_3 DEFINE 0x10
SBAUDF_4 DEFINE 0x20
SBAUDF_5 DEFINE 0x40
UARTBAUDEN DEFINE 0x80
//SBAUDT
DIV0 DEFINE 0x01
DIV1 DEFINE 0x02
DIV2 DEFINE 0x04
SBTH0 DEFINE 0x08
SBTH1 DEFINE 0x10
BE DEFINE 0x20
FE DEFINE 0x40
OWE DEFINE 0x80
//SBAUD2
DIV2_0 DEFINE 0x01
DIV2_1 DEFINE 0x02
DIV2_2 DEFINE 0x04
SBTH2_0 DEFINE 0x08
SBTH2_1 DEFINE 0x10
SBF2 DEFINE 0x20
RB28 DEFINE 0x40
TB28 DEFINE 0x80
//SCON2
RI2 DEFINE 0x01
TI2 DEFINE 0x02
REN2 DEFINE 0x04
BE2 DEFINE 0x08
FE2 DEFINE 0x10
OWE2 DEFINE 0x20
EN_T8 DEFINE 0x40
//EPFG
MOD38_CF2 DEFINE 0x01
MOD38_MISO DEFINE 0x02
MOD38_SSb DEFINE 0x04
MOD38_CF1 DEFINE 0x08
MOD38_TxD DEFINE 0x10
MOD38_FP23 DEFINE 0x20
MOD38_FP22 DEFINE 0x40
MOD38_FP21 DEFINE 0x80
//TMOD
T0_M0 DEFINE 0x01
T0_M1 DEFINE 0x02
C_T0 DEFINE 0x04
GATE0 DEFINE 0x08
T1_M0 DEFINE 0x10
T1_M1 DEFINE 0x20
C_T1 DEFINE 0x40
GATE1 DEFINE 0x80
#endif /* __IAR_SYSTEMS_ASM__*/
#endif /* IOADE7169F16_H */
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