📄 warning.asm
字号:
;;IC Body:BM22P02
;*****************************************************************************
; Case Name: 定时报警器 *
; Version: 1.0 *
; Ooooo Author : Cao ChaoHao(Iceman) *
; ooooO ( ) E-mail : Iceman_cch@yahoo.com.cn *
; ( ) ) / Tel : (86)021-54272266-303 13621800227 *
; \ ( (_/ Fax : (86)021-54264402 *
; \_) Date : 2008/10/16 *
; Company: Shanghai Belling-Systron *
; Web : http://www.systron.sh.cn *
;*****************************************************************************
PORT0 EQU $00
DDR0 EQU $01 ;P0口方向寄存器(0为输入口,1为输出口)
P0HCON EQU $02 ;P0口上拉控制(0上拉电阻无效,1有效)
P0LCON EQU $03 ;P0口下拉控制(0下拉电阻无效,1有效)
PORT1 EQU $04
DDR1 EQU $05
P1HCON EQU $06
KBIM EQU $07
PORT2 EQU $08
DDR2 EQU $09
TDR EQU $0A
TCR EQU $0B
P0PND EQU $0C
MCR EQU $0D
RSTFR EQU $0E
; PORT0
P00 EQU 0 ;INT0
P01 EQU 1 ;INT1
P02 EQU 2
P03 EQU 3
P04 EQU 4
P05 EQU 5
P06 EQU 6
P07 EQU 7
;PORT1
P10 EQU 0
P11 EQU 1
P12 EQU 2
P13 EQU 3
P14 EQU 4
P15 EQU 5
P16 EQU 6 ;TCC
P17 EQU 7 ;RST/VPP
;PORT2
P20 EQU 0 ;OSCI
P21 EQU 1 ;OSCO
;DDR0 ;PORT0口方向寄存器
DDRA0 EQU 0
DDRA1 EQU 1
DDRA2 EQU 2
DDRA3 EQU 3
DDRA4 EQU 4
DDRA5 EQU 5
DDRA6 EQU 6
DDRA7 EQU 7
;DDR1 ;PORT1口方向寄存器
DDRB0 EQU 0 ;当TCR中PTS=1时,P16被置为输入口,DDR1[6]无效
DDRB1 EQU 1
DDRB2 EQU 2
DDRB3 EQU 3
DDRB4 EQU 4
DDRB5 EQU 5
DDRB6 EQU 6
;KBIM ;键盘中断寄存器
KBE0 EQU 0 ;(P10:P16 1键盘中断功能打开,0关闭)
KBE1 EQU 1 ;键盘中断功能打开,自动将P1[i]置为输入
KBE2 EQU 2 ;使用键盘中断功能,还必须将KBIE位置1
KBE3 EQU 3 ;当TCR中PTS=1时,KBE[6]无效
KBE4 EQU 4
KBE5 EQU 5
KBE6 EQU 6
;TDR ;定时器数据寄存器
TD0 EQU 0
TD1 EQU 1
TD2 EQU 2
TD3 EQU 3
TD4 EQU 4
TD5 EQU 5
TD6 EQU 6
TD7 EQU 7
;TCR ;定时器控制寄存器
PTE EQU 0 ;TCC信号沿选择(0:当TCC引脚由低到高变化时计数器减1;1:当TCC引脚由高到低变化时计数器减1)
PTS EQU 1 ;TCC信号源选择(0:内部周期时钟;1:TCC引脚状态变化)
PTA EQU 2 ;预除器分配位(0:预除器分配给TCC;1:预除器分配给WDT)
PR0 EQU 3 ;TCC/WDT预分频器分频率的选择位
PR1 EQU 4
PR2 EQU 5
TMI EQU 6 ;0:定时器中断允许;1:定时器中断禁止
TIF EQU 7 ;0:定时器未溢出;1: 定时器溢出
;定时器的计数器一旦计数结果为“0”,则把TIF置“1”,表示有定时器中断请求,
;系统复位或对TIF写“0”可以将TIF清零.
;PR2 PR1 PR0 TCC WDT
; 0 0 0 2 1
; 0 0 1 4 2
; 0 1 0 8 4
; 0 1 1 16 8
; 1 0 0 32 16
; 1 0 1 64 32
; 1 1 0 128 64
; 1 1 1 256 128
;P0PND
INT1F EQU 0
INT1M0 EQU 1
INT1M1 EQU 2 ;.2-.1 INT1M 00 中断触发设置
;00: 下降沿触发;01:上升沿触发
;10:低电平触发;11:高电平触发
INT1E EQU 3 ;INT1使能位(0关闭;1打开)
INT0F EQU 4
INT0M0 EQU 5
INT0M1 EQU 6
;00: 下降沿触发;01:上升沿触发
;10:低电平触发;11:高电平触发
;INT1E EQU 7 ;INT0使能位(0关闭;1打开)
;MCR
USEL EQU 1 ;0:当DDR2[1]=1时,P21输出P2[1]寄存器值
;1:当DDR2[1]=1时,P21输出系统时钟
WDTM EQU 2 ;0:WDT溢出复位;1:WDT溢出唤醒STOP
WDTF EQU 3 ;0:WDT未溢出;1:WDT溢出
WDTC EQU 4 ;读WDTC始终为0;写0能清WDT计数器;写1无效
WDTE EQU 5 ;0:WDT有效;1:WDT无效
KBIC EQU 6 ;0:保留键盘中断锁存信号;1:清除键盘中断锁存信号
KBIE EQU 7 ;0:键盘中断禁止;1:键盘中断允许
;RSTFR ;Reset Flag Register
RSTF0 EQU 0 ;0:无上电复位;1:有上电复位;写0清标志,写1无效
RSTF1 EQU 1 ;0:无RES引脚复位;1:有RES引脚复位;写0清标志,写1无效
RSTF2 EQU 2 ;0:无LVR复位;1:有LVR复位;写0清标志,写1无效
RSTF3 EQU 3 ;0:无WDT复位;1:有WDT复位;写0清标志,写1无效
;上电复位时,除RSTF0被置为1外,其他3位都置0;另3种复位不会影响其他位.
MARK EQU $C0
T_1S EQU 0
T_2S EQU 1
T_S EQU 2
BUZZER EQU 3
COUNTER1 EQU $C1
COUNTER2 EQU $C2
MODE_CNT EQU $C3
ORG $1800
RESET: ;上电复位
SEI
RSP
Start:
BSET WDTE,MCR
BCLR WDTC,MCR
LDA #$FF
STA DDR0
STA DDR1
CLR PORT0
CLR PORT1
CLR MARK
CLR COUNTER1
CLR COUNTER2
LDA #%00111000 ;
STA TCR ;开启定时器中断,256分频,预分频给TCC
LDA #64
STA TDR ;64×256×2÷32768=1S
CLI
MAIN:
LDA MODE_CNT
CMP #0
BEQ MODE1
CMP #1
BEQ MODE2
CMP #2
BEQ MODE3
JMP MODE4
MODE1:
BSET P16,PORT1 ;绿灯长亮
BRCLR T_1S,MARK,MODE1_RETURN
BCLR T_1S,MARK
INC COUNTER1
LDA COUNTER1
CMP #30
BNE MODE1_RETURN
CLR COUNTER1
INC COUNTER2
LDA COUNTER2
CMP #30
BNE MODE1_RETURN
CLR COUNTER2
CLR MARK
INC MODE_CNT
MODE1_RETURN:
JMP MAIN
MODE2:
BCLR P16,PORT1
BRCLR T_1S,MARK,MODE2_RETURN
BCLR T_1S,MARK
BRSET T_2S,MARK,MODE21
BSET T_2S,MARK
BSET P07,PORT0 ;红灯0.5Hz
MODE22:
INC COUNTER1
LDA COUNTER1
CMP #30
BNE MODE2_RETURN
CLR COUNTER1
INC COUNTER2
LDA COUNTER2
CMP #30
BNE MODE2_RETURN
CLR COUNTER2
CLR MARK
INC MODE_CNT
MODE2_RETURN:
JMP MAIN
MODE21:
BCLR P07,PORT0
BCLR T_2S,MARK
JMP MODE22
MODE3:
BRSET BUZZER,MARK,BUZZER0
JSR DELAY_500MS
BSET P07,PORT0
MODE32:
NOP
BRCLR T_1S,MARK,MODE32
BCLR T_1S,MARK
BCLR P07,PORT0
MODE31:
INC COUNTER1
LDA COUNTER1
CMP #15 ;15S
BNE MODE3_RETURN
CLR COUNTER1
BSET BUZZER,MARK
INC COUNTER2
LDA COUNTER2
CMP #120
BNE MODE3_RETURN
CLR COUNTER2
CLR MARK
INC MODE_CNT
MODE3_RETURN:
JMP MAIN
BUZZER0:
JSR DELAY_50MS
JSR DELAY_50MS ;100MS
JSR DELAY_50MS
JSR DELAY_50MS ;200MS
JSR DELAY_50MS
JSR DELAY_50MS ;300MS
JSR DELAY_50MS
JSR DELAY_50MS ;400MS
JSR DELAY_50MS
JSR DELAY_50MS ;500MS
BSET P07,PORT0
JSR DELAY_50MS
JSR DELAY_50MS ;600MS
JSR DELAY_50MS
JSR DELAY_50MS ;700MS
JSR DELAY_50MS
JSR DELAY_50MS ;800MS
JSR DELAY_50MS
JSR DELAY_50MS ;900MS
JSR DELAY_50MS
JSR DELAY_50MS ;1000MS
BCLR P07,PORT0
BCLR BUZZER,MARK
INC COUNTER1
JMP MAIN
MODE4:
BRSET BUZZER,MARK,BUZZER1
JSR DELAY_500MS
BSET P07,PORT0
MODE42:
NOP
BRCLR T_1S,MARK,MODE42
BCLR T_1S,MARK
BCLR P07,PORT0
MODE_41:
INC COUNTER1
LDA COUNTER1
CMP #5
BNE MODE4_RETURN
CLR COUNTER1
BSET BUZZER,MARK
MODE4_RETURN:
JMP MAIN
BUZZER1:
JSR DELAY_50MS
JSR DELAY_50MS ;100MS
JSR DELAY_50MS
JSR DELAY_50MS ;200MS
JSR DELAY_50MS
JSR DELAY_50MS ;300MS
JSR DELAY_50MS
JSR DELAY_50MS ;400MS
JSR DELAY_50MS
JSR DELAY_50MS ;500MS
BSET P07,PORT0
BCLR BUZZER,MARK
JMP MAIN
DELAY_500MS: ;(32*248+2+6=134)*0.06104=490MS
LDX #248 ;2
LOOP:
NOP ;4
NOP
NOP ;4
NOP
NOP ;4
NOP
NOP ;4
NOP
NOP ;4
NOP
NOP ;4
NOP
NOP ;2
DECX ;3
BNE LOOP ;3
RTS ;6
DELAY_50MS:
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5*61
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
BSET P00,PORT0 ;5
BCLR P00,PORT0 ;5
RTS
WDTI:
BCLR WDTC,MCR
RTI
KBI:
BSET KBIC,MCR
RTI
TMINTERRUPT: ;1S中断
BCLR TIF,TCR
LDA TDR
ADD #64 ;计数初值64
STA TDR
BSET T_1S,MARK
RTI
ORG $1FF2
FDB WDTI
ORG $1FF4
FDB KBI
ORG $1FF6
FDB TMINTERRUPT
ORG $1FFE
FDB RESET
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