video_ntsc_pal.c

在海尔的DM642开发板实现RF5框架

/*
 *  Copyright 2003 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  
 */
/* "@(#) DDK 1.10.00.23 07-02-03 (ddk-b12)" */
#include <std.h>
#include <log.h>
#include <sys.h>
#include <mem.h>
#include <sio.h>
#include <tsk.h>


#include <csl.h>
#include <csl_dat.h>
#include <csl_cache.h>
#include <csl_i2c.h>
#include <csl_emifa.h>
#include <csl_gpio.h>
//==============//
/*#include <csl_mcasp.h>*/
//-===========-//

#include <fvid.h>
#include <edc.h>
#include <vport.h>
#include <vportcap.h>
#include <vportdis.h>
#include <tvp5150.h>
#include <tvp6000.h>
    
#include "appData.h"
#include "evmdm642.h"
#include "evmdm642_vcapparams.h"
#include "evmdm642_vdisparams.h" 


#define BUFLEN 		2403    /* number of samples in the frame */
#define BUFALIGN 	128    /* alignment of buffer to allow use of L2 cache */

#define BUFSIZE (BUFLEN * sizeof(MdUns)) 

/* I2C handle */
I2C_Handle EVMDM642_I2C_hI2C;

/* GPIO handle */
GPIO_Handle EVMDM642_GPIO_hGPIO;

/* inStream and outStream are SIO handles created in main */
SIO_Handle inStream, outStream;

/* heap IDs defined in the BIOS configuration file */

/*
 * ======== main ========
 */
main()
{
 //   EVMDM642_init();
 
  CSL_init();                                             
    CACHE_clean(CACHE_L2ALL, 0, 0);
    CACHE_setL2Mode(CACHE_64KCACHE);       
    CACHE_enableCaching(CACHE_EMIFA_CE00);
    CACHE_enableCaching(CACHE_EMIFA_CE01);
   
    CACHE_setL2Queue(CACHE_L2Q0,7);
	CACHE_setL2Queue(CACHE_L2Q1,7);
	CACHE_setL2Queue(CACHE_L2Q2,7);
	CACHE_setL2Queue(CACHE_L2Q3,7);
    

    CACHE_setPriL2Req(CACHE_L2PRILOW); 
    DAT_open(DAT_CHAANY, DAT_PRI_LOW, DAT_OPEN_2D);
    //Fat32_install ();

    appThreadInit();
	
	

}




/* Spin in a delay loop for delay iterations */
void EVMDM642_wait(Uint32 delay)
{
	volatile Uint32 i, n;
	
	n = 0;
	for (i = 0; i < delay; i++)
	{
	    n = n + 1;
	}
}

/* Initialize the board APIs */
void EVMDM642_init()
{
    volatile Uint32 test;
    //-=================-//
//	MCASP_Handle handle;
	//-================-//
#if 0    
	I2C_Config i2cCfg = {
		0x0000007f, /* I2COAR -    Not used if master */
		0x00000000, /* I2CIER -    Disable interrupts, use polling */
		0x0000001b, /* I2CCLKL -   Low period for 100KHz operation */
		0x0000001b, /* I2CCLKH -   High period for 100KHz operation */
		0x00000002, /* I2CCNT -    Data words per transmission */
		0x0000001a, /* I2CSAR -    Slave address */
		//0x00004620, /* I2CMDR -    Mode 4680*/
		0x00004780,	//0x00004680, /* I2CMDR -    Mode */
		0x00000019  /* I2CPSC -    Prescale 300MHz to 12MHz */
	};
#else
#if 0
	I2C_Config i2cCfg = {	
	    0,  /* master mode,  i2coar;   */
	    0,  /* no interrupt, i2cimr;   */
	    (20-5), /* scl low time, i2cclkl;  */
	    (20-5), /* scl high time,i2cclkh;  */
	    1,  /* configure later, i2ccnt;*/
	    0,  /* configure later, i2csar;*/
	    0x046a0, /* master tx mode,     */
	            /* i2c runs free,      */
	            /* 8-bit data + NACK   */
	            /* no repeat mode      */
	    (75-1), /* 4MHz clock, i2cpsc  */
    };
#else
	I2C_Config i2cCfg = {	
		0x0000007f, /* I2COAR -    Not used if master */
		0x00000000, /* I2CIER -    Disable interrupts, use polling */
		0x0000001b, /* I2CCLKL -   Low period for 100KHz operation */
		0x0000001b, /* I2CCLKH -   High period for 100KHz operation */
		0x00000000, /* I2CCNT -    Data words per transmission */
		0x00000000, /* I2CSAR -    Slave address */
		0x00004680,	/* I2CMDR -    Mode */
		0x0000004a  /* I2CPSC -    Prescale 300MHz to 12MHz */
    };    
#endif
#endif
	/* Initialize CSL */
	CSL_init();
	
	/* EMIFA */
	*(int *)EVMDM642_EMIFA_GCTL     = 0x00052078;
	*(int *)EVMDM642_EMIFA_CE0      = 0xffffffd3;  /* CE0 SDRAM                     */
	*(int *)EVMDM642_EMIFA_CE1      = 0x73a28e01;  /* CE1 Flash + CPLD              */
	*(int *)EVMDM642_EMIFA_CE2      = 0xffffffc3;  /* CE2 Daughtercard 32-bit async */
	*(int *)EVMDM642_EMIFA_CE3      = 0x22a28a42;  /* CE3 Daughtercard 32-bit sync  */
	*(int *)EVMDM642_EMIFA_SDRAMCTL = 0x57116000;  /* SDRAM control                 */
	*(int *)EVMDM642_EMIFA_SDRAMTIM = 0x0000081b;  /* SDRAM timing (refresh)        */
	*(int *)EVMDM642_EMIFA_SDRAMEXT = 0x001faf4d;  /* SDRAM extended control        */
	*(int *)EVMDM642_EMIFA_CE0SECCTL= 0x00000002;  /* CE0 Secondary Control Reg.    */
	*(int *)EVMDM642_EMIFA_CE1SECCTL= 0x00000002;  /* CE1 Secondary Control Reg.    */
	*(int *)EVMDM642_EMIFA_CE2SECCTL= 0x00000002;  /* CE2 Secondary Control Reg.    */
	*(int *)EVMDM642_EMIFA_CE3SECCTL= 0x00000073;  /* CE3 Secondary Control Reg.    */
	
	/************************************************************************/ 
	/* (DEVSTAT)  0x01b3f004 -- Device Status Register 						*/
	/* (JTAGID)   0x01b3f008 -- JTAG Identification Register 				*/
	/* (PERCFG)   0x01b3f000 -- Peripheral Configuration Register			*/
	/* (PCFGLOCK) 0x01b3f018 -- Peripheral Configuration Lock Register		*/
	/************************************************************************/
	/* Unlock PERCFG through PCFGLOCK */
	EVMDM642_PCFGLOCK = 0x10c0010c;
	//test = EVMDM642_DEVSTAT;	
	/* Enable VP0-VP2, I2C in PERCFG */
	EVMDM642_PERCFG = 0x79;
	
	/* Read back PERCFG */
	test = EVMDM642_PERCFG;
	
	/* Wait at least 128 CPU cycles */
	EVMDM642_wait(128);
	
	/* Open I2C handle */
	EVMDM642_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);
	
	/* Configure I2C controller */
	I2C_config(EVMDM642_I2C_hI2C, &i2cCfg);
	
	/* Take I2C out of reset */        
	I2C_outOfReset(EVMDM642_I2C_hI2C);
	                                          
	/* Open the GPIO handle */
	EVMDM642_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET);
	
	/* Enable caching of SDRAM */
	
	DAT_open(DAT_CHAANY, DAT_PRI_LOW, DAT_OPEN_2D);   //???usage??of this func? 
	//==============================================//
//	handle = MCASP_open(0, MCASP_OPEN_RESET);
//	MCASP_enableSers(handle, MCASP_RCV);
//        while (!MCASP_FGETH(handle, GBLCTL, RSRCLR));
        //=================================================//
    /* Configure APLL in default state */
//    EVMDM642_APLL_rset(EVMDM642_APLL_FSG0);

}


/* Read an 8-bit value from a CPLD register */
Uint8 EVMDM642_rget(Int16 regnum)
{
    Uint8 *pdata;
    
    /* Return lower 8 bits of register */
    pdata = (Uint8 *)(EVMDM642_CPLD_BASE + regnum);
    return (*pdata & 0xff);
}

/* Write an 8-bit value to a CPLD register */
void EVMDM642_rset(Int16 regnum, Uint8 regval)
{
    Uint8 *pdata;
    
    /* Write lower 8 bits of register */
    pdata = (Uint8 *)(EVMDM642_CPLD_BASE + regnum);
    *pdata = (regval & 0xff);
}

/* Spin in a delay loop for delay microseconds */
void EVMDM642_waitusec(Uint32 delay)
{
    EVMDM642_wait(delay * 21);
}

/* Write to the configuration register on the analog PLL */
void EVMDM642_APLL_rset(Uint16 data)
{
    /* Write data to the APLL */
    *((volatile Uint32 *)(EVMDM642_SYNC_BASE + 4)) = data;

    /* Wait for transmission to complete */
    while ((EVMDM642_rget(EVMDM642_ISR) & 0x20) == 0);
}