video_ntsc_pal_back.c

在海尔的DM642开发板实现RF5框架

/*
 *  Copyright 2003 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  
 */
/* "@(#) DDK 1.10.00.23 07-02-03 (ddk-b12)" */
#include <std.h>
#include <tsk.h>  
#include <sem.h>   
#include <gio.h>

#include <csl_dat.h>
#include <csl_cache.h>
#include <csl_i2c.h>

#include <fvid.h>
#include <edc.h>
#include <vport.h>
#include <vportcap.h>
#include <vportdis.h>
#include <tvp5150.h>
#include <tvp6000.h>    

#include <evmdm642.h>
#include "COLORBAR.h"
#include "evmdm642_vcapparams.h"
#include "evmdm642_vdisparams.h" 
#include "CIF.h"  

#define EMIFA_GCTL       0x01800000
#define EMIFA_CE1        0x01800004
#define EMIFA_CE0        0x01800008
#define EMIFA_CE2        0x01800010
#define EMIFA_CE3        0x01800014
#define EMIFA_SDRAMCTL   0x01800018
#define EMIFA_SDRAMTIM   0x0180001c
#define EMIFA_SDRAMEXT   0x01800020
#define EMIFA_CE1SECCTL  0x01800044
#define EMIFA_CE0SECCTL  0x01800048
#define EMIFA_CE2SECCTL  0x01800050
#define EMIFA_CE3SECCTL  0x01800054

/* I2C handle */
I2C_Handle EVMDM642_I2C_hI2C;

/* GPIO handle */
GPIO_Handle EVMDM642_GPIO_hGPIO;

/* heap IDs defined in the BIOS configuration file */
extern Int EXTERNALHEAP;

/*
 * ======== main ========
 */
main()
{
    EVMDM642_init();
}

/*
 * ======== tskVideo_LOOPBACK ========
 * video _LOOPBACK function.
 */
void tskVideoLoopback()
{
    int i;
	
    Int status;
    FVID_Handle dis_Chan; 
    Int frames = 0;
    FVID_Frame *dis_FrameBuf;
    Int numLinesDis = EVMDM642_vDisParamsChan.imgVSizeFld1; //287
    Int numLinesCap = EVMDM642_vCapParamsChan.fldYStop1 -  
       EVMDM642_vCapParamsChan.fldYStrt1 + 1;			//288-1

    Int numLines = (numLinesDis > numLinesCap) ? numLinesCap : numLinesDis;
	
    FVID_Handle cap1_Chan; 
    Int numPixels = EVMDM642_vCapParamsChan.fldXStop1 -   //720
       EVMDM642_vCapParamsChan.fldXStrt1+1;
    FVID_Frame *cap1_FrameBuf;
    Int capLinePitch = EVMDM642_vCapParamsChan.fldXStop1 - 
       EVMDM642_vCapParamsChan.fldXStrt1+1;
    Int disLinePitch = EVMDM642_vDisParamsChan.imgHSizeFld1;

    numLines *= 2; /* both fields */
    /******************************************************/
    /* allocate both capture and display frame buffers    */
    /* in external heap memory                            */
    /******************************************************/
	EVMDM642_vCapParamsChan.segId = EXTERNALHEAP;
	EVMDM642_vDisParamsChan.segId = EXTERNALHEAP;
	EVMDM642_vDisParamsTVP6000.hI2C = EVMDM642_I2C_hI2C;
	EVMDM642_vCapParamsTVP5150.hI2C = EVMDM642_I2C_hI2C;

    /******************************************************/
    /* initialization of capture driver                   */
    /******************************************************/
    cap1_Chan = FVID_create("/VP0CAPTURE/A/0", 
	            IOM_INPUT, &status, (Ptr)&EVMDM642_vCapParamsChan, NULL);
    
    /******************************************************/
    /* initialization of display driver                   */
    /******************************************************/
    dis_Chan = FVID_create("/VP2DISPLAY", IOM_OUTPUT, 
        &status, (Ptr)&EVMDM642_vDisParamsChan, NULL);

    /******************************************************/
    /* configure video encoder & decoder                  */
    /******************************************************/
    FVID_control(dis_Chan, VPORT_CMD_EDC_BASE + EDC_CONFIG, 
        (Ptr)&EVMDM642_vDisParamsTVP6000);
	
    FVID_control(cap1_Chan, VPORT_CMD_EDC_BASE + EDC_CONFIG, 
	        (Ptr)&EVMDM642_vCapParamsTVP5150);
    /******************************************************/
    /* start capture & display operation                  */    
    /******************************************************/
    FVID_control(dis_Chan, VPORT_CMD_RESET, NULL);
    FVID_control(dis_Chan, VPORT_CMD_START, NULL);
    FVID_control(cap1_Chan, VPORT_CMD_START, NULL);
    /********************************************************/
    /* request a frame buffer from display & capture driver */
    /********************************************************/
    FVID_alloc(dis_Chan, &dis_FrameBuf);
    FVID_alloc(cap1_Chan, &cap1_FrameBuf);
	
	while(1){/* loop forever */
	    /* copy data from capture buffer to display buffer */
	    /***************************************************/
	    for(i = 0; i < numLines; i ++) {
	        DAT_copy(cap1_FrameBuf->frame.iFrm.y1 + i * capLinePitch, 
	                 dis_FrameBuf->frame.iFrm.y1 + i * disLinePitch,
	                 numPixels);
	        DAT_copy(cap1_FrameBuf->frame.iFrm.cb1 + i * (capLinePitch >> 1), 
	                 dis_FrameBuf->frame.iFrm.cb1 + i * (disLinePitch >> 1),
	                 numPixels>>1);
	
	        DAT_copy(cap1_FrameBuf->frame.iFrm.cr1 + i * (capLinePitch >> 1), 
	                 dis_FrameBuf->frame.iFrm.cr1 + i * (disLinePitch >> 1),
	                 numPixels>>1);
	    }
	   	DAT_wait(DAT_XFRID_WAITALL);
	    FVID_exchange(cap1_Chan, &cap1_FrameBuf);
	    FVID_exchange(dis_Chan, &dis_FrameBuf);        
	
	 if(frames < 256) frames ++;              
	 else frames = 0;
	}
}

/* Spin in a delay loop for delay iterations */
void EVMDM642_wait(Uint32 delay)
{
	volatile Uint32 i, n;
	
	n = 0;
	for (i = 0; i < delay; i++)
	{
	    n = n + 1;
	}
}

/* Initialize the board APIs */
void EVMDM642_init()
{
    volatile Uint32 test;

	I2C_Config i2cCfg = {
		0x0000007f, /* I2COAR -    Not used if master */
		0x00000000, /* I2CIER -    Disable interrupts, use polling */
		0x0000001b, /* I2CCLKL -   Low period for 100KHz operation */
		0x0000001b, /* I2CCLKH -   High period for 100KHz operation */
		0x00000002, /* I2CCNT -    Data words per transmission */
		0x0000001a, /* I2CSAR -    Slave address */
		//0x00004620, /* I2CMDR -    Mode 4680*/
		0x00004680, /* I2CMDR -    Mode */
		0x00000019  /* I2CPSC -    Prescale 300MHz to 12MHz */
	};
        
	/* EMIFA */
	*(int *)EMIFA_GCTL     = 0x00052078;
	*(int *)EMIFA_CE0      = 0xffffffd3;  /* CE0 SDRAM                     */
	*(int *)EMIFA_CE1      = 0x73a28e01;  /* CE1 Flash + CPLD              */
	*(int *)EMIFA_CE2      = 0xffffffc3;  /* CE2 Daughtercard 32-bit async */
	*(int *)EMIFA_CE3      = 0x22a28a42;  /* CE3 Daughtercard 32-bit sync  */
	*(int *)EMIFA_SDRAMCTL = 0x57228000;  /* SDRAM control                 */
	*(int *)EMIFA_SDRAMTIM = 0x0000081b;  /* SDRAM timing (refresh)        */
	*(int *)EMIFA_SDRAMEXT = 0x001faf4d;  /* SDRAM extended control        */
	*(int *)EMIFA_CE0SECCTL= 0x00000002;  /* CE0 Secondary Control Reg.    */
	*(int *)EMIFA_CE1SECCTL= 0x00000002;  /* CE1 Secondary Control Reg.    */
	*(int *)EMIFA_CE2SECCTL= 0x00000002;  /* CE2 Secondary Control Reg.    */
	*(int *)EMIFA_CE3SECCTL= 0x00000073;  /* CE3 Secondary Control Reg.    */
	     
	/* Initialize CSL */
	CSL_init();
	
	/* Unlock PERCFG through PCFGLOCK */
	*((unsigned long *)0x1b3f018) = 0x10c0010c;
	
	/* Enable VP0-VP2, I2C and McASP0 in PERCFG */
	*((unsigned long *)0x1b3f000) = 0x79;
	
	/* Read back PERCFG */
	test = *((unsigned long *)0x1b3f000);
	
	/* Wait at least 128 CPU cycles */
	EVMDM642_wait(128);
	
	/* Open I2C handle */
	EVMDM642_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);
	
	/* Configure I2C controller */
	I2C_config(EVMDM642_I2C_hI2C, &i2cCfg);
	
	/* Take I2C out of reset */        
	I2C_outOfReset(EVMDM642_I2C_hI2C);
	                                          
	/* Open the GPIO handle */
	EVMDM642_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET);
	
	/* Enable caching of SDRAM */
	CACHE_clean(CACHE_L2ALL, 0, 0);
	CACHE_setL2Mode(CACHE_256KCACHE);       
	CACHE_enableCaching(CACHE_EMIFA_CE00);
	CACHE_enableCaching(CACHE_EMIFA_CE01);
	DAT_open(DAT_CHAANY, DAT_PRI_LOW, DAT_OPEN_2D);    
}