📄 tsk_audio.c
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Int numLinesCap = EVMDM642_vCapParamsChan.fldYStop1 - //288-1
EVMDM642_vCapParamsChan.fldYStrt1 + 1;
Int numLines = (numLinesDis > numLinesCap) ? numLinesCap : numLinesDis;
Int numPixels = EVMDM642_vCapParamsChan.fldXStop1 - //720
EVMDM642_vCapParamsChan.fldXStrt1+1;
Int capLinePitch = EVMDM642_vCapParamsChan.fldXStop1 -
EVMDM642_vCapParamsChan.fldXStrt1+1;
Int disLinePitch = EVMDM642_vDisParamsChan.imgHSizeFld1;
numLines *= 2; /* both fields */
/******************************************************/
/* allocate both capture and display frame buffers */
/* in external heap memory */
/******************************************************/
EVMDM642_vCapParamsChan.segId = extHeap;
EVMDM642_vDisParamsChan.segId = extHeap;
EVMDM642_vDisParamsTVP6000.hI2C = EVMDM642_I2C_hI2C;
EVMDM642_vCapParamsTVP5150.hI2C = EVMDM642_I2C_hI2C;
/******************************************************/
/* initialization of capture driver */
/******************************************************/
cap1_Chan = FVID_create("/VP0CAPTURE/A/0",
IOM_INPUT, &status, (Ptr)&EVMDM642_vCapParamsChan, NULL);
cap2_Chan = FVID_create("/VP1CAPTURE/A/1",
IOM_INPUT, &status, (Ptr)&EVMDM642_vCapParamsChan, NULL);
/******************************************************/
/* initialization of display driver */
/******************************************************/
dis_Chan = FVID_create("/VP2DISPLAY",
IOM_OUTPUT, &status, (Ptr)&EVMDM642_vDisParamsChan, NULL);
/******************************************************/
/* configure video encoder & decoder */
/******************************************************/
// EVMDM642_rset(0x10, 0x20);
// EVMDM642_rset(0x10, 0x08);
// while(!(EVMDM642_rget(0x13) & 0x40));
//FVID_control(cap1_Chan, VPORT_CMD_CONFIG_PORT, NULL);
FVID_control(dis_Chan, VPORT_CMD_EDC_BASE + EDC_CONFIG,
(Ptr)&EVMDM642_vDisParamsTVP6000);
FVID_control(cap1_Chan, VPORT_CMD_EDC_BASE + EDC_CONFIG,
(Ptr)&EVMDM642_vCapParamsTVP5150);
FVID_control(cap2_Chan, VPORT_CMD_EDC_BASE + EDC_CONFIG,
(Ptr)&EVMDM642_vCapParamsTVP5150);
/******************************************************/
/* start capture & display operation */
/******************************************************/
FVID_control(dis_Chan, VPORT_CMD_START, NULL);
FVID_control(cap1_Chan, VPORT_CMD_START, NULL);
FVID_control(cap2_Chan, VPORT_CMD_START, NULL);
// for(;;);
/********************************************************/
/* request a frame buffer from display & capture driver */
/********************************************************/
FVID_alloc(dis_Chan, &dis_FrameBuf);
FVID_alloc(cap1_Chan, &cap1_FrameBuf);
FVID_alloc(cap2_Chan, &cap2_FrameBuf);
while(1)
{/* loop forever */
/* copy data from capture buffer to display buffer */
/***************************************************/
for(i = 0; i < numLines; i ++) {
DAT_copy(cap1_FrameBuf->frame.iFrm.y1 + i * capLinePitch,
dis_FrameBuf->frame.iFrm.y1 + i * disLinePitch,
numPixels);
DAT_copy(cap1_FrameBuf->frame.iFrm.cb1 + i * (capLinePitch >> 1),
dis_FrameBuf->frame.iFrm.cb1 + i * (disLinePitch >> 1),
numPixels>>1);
DAT_copy(cap1_FrameBuf->frame.iFrm.cr1 + i * (capLinePitch >> 1),
dis_FrameBuf->frame.iFrm.cr1 + i * (disLinePitch >> 1),
numPixels>>1);
}
DAT_wait(DAT_XFRID_WAITALL);
FVID_exchange(cap1_Chan, &cap1_FrameBuf);
FVID_exchange(dis_Chan, &dis_FrameBuf);
TSK_sleep(10);
if (on_off == 1)
{
FVID_control(dis_Chan, VPORT_CMD_EDC_BASE + TVP6000_SET_USER,
(Ptr)&EVMDM642_vDisParamsTVP6000);
on_off = 0;
}
if(frames < 256) frames ++;
else frames = 0;
}
#endif
}
/***************************************************************************
* Function: EVMDM642_init
* Description: Initialize the board APIs
* Calls:
* Calls by: main
* Input: none
* Output: none
* Return: none
* Create by: david
* Date: 2004.03.08
* History:
* Version: 1.0
****************************************************************************/
void EVMDM642_init()
{
volatile Uint32 test;
/* Initialize CSL */
CSL_init();
/* EMIFA */
*(int *)EVMDM642_EMIFA_GCTL = 0x00052078;
*(int *)EVMDM642_EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
*(int *)EVMDM642_EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
*(int *)EVMDM642_EMIFA_CE2 = 0xffffffc3; /* CE2 Daughtercard 32-bit async */
*(int *)EVMDM642_EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard 32-bit sync */
*(int *)EVMDM642_EMIFA_SDRAMCTL = 0x57116000; /* SDRAM control */
*(int *)EVMDM642_EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing (refresh) */
*(int *)EVMDM642_EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended control */
*(int *)EVMDM642_EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control Reg. */
*(int *)EVMDM642_EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control Reg. */
*(int *)EVMDM642_EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control Reg. */
*(int *)EVMDM642_EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control Reg. */
EVMDM642_I2C_init();
/* Open the GPIO handle */
EVMDM642_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET);
/* Enable caching of SDRAM */
CACHE_clean(CACHE_L2ALL, 0, 0);
CACHE_setL2Mode(CACHE_64KCACHE);
CACHE_enableCaching(CACHE_EMIFA_CE00);
CACHE_enableCaching(CACHE_EMIFA_CE01);
DAT_open(DAT_CHAANY, DAT_PRI_LOW, DAT_OPEN_2D);
CACHE_setPriL2Req(CACHE_L2PRIHIGH);
#define L2ALLOC3 0x0184200C
*(int *) L2ALLOC3 = (*(int *) L2ALLOC3) | 0x00000007;
#define L2ALLOC2 0x01842008
*(int *) L2ALLOC2 = (*(int *) L2ALLOC2) | 0x00000007;
#define L2ALLOC1 0x01842004
*(int *) L2ALLOC1 = (*(int *) L2ALLOC1) | 0x00000007;
/* Configure APLL in default state */
// EVMDM642_APLL_rset(EVMDM642_APLL_FSG0);
}
/***************************************************************************
* Function: EVMDM642_wait
* Description: Spin in a delay loop for delay iterations
* Calls: EVMDM642_rget
* Calls by: main
* Input: none
* Output: none
* Return: none
* Create by: david
* Date: 2004.03.08
* History:
* Version: 1.0
****************************************************************************/
void EVMDM642_wait(Uint32 delay)
{
volatile Uint32 i, n;
n = 0;
for (i = 0; i < delay; i++)
{
n = n + 1;
}
}
/***************************************************************************
* Function: EVMDM642_waitusec
* Description: Spin in a delay loop for delay microseconds
* Calls: EVMDM642_wait
* Calls by: main
* Input: none
* Output: none
* Return: none
* Create by: david
* Date: 2004.03.08
* History:
* Version: 1.0
****************************************************************************/
void EVMDM642_waitusec(Uint32 delay)
{
EVMDM642_wait(delay * 21);
}
/***************************************************************************
* Function: EVMDM642_I2C_init
* Description: initialize the dm642 i2c
* Calls:
* Calls by: main
* Input: none
* Output: none
* Return: none
* Create by: david
* Date: 2004.03.08
* History:
* Version: 1.0
****************************************************************************/
void EVMDM642_I2C_init()
{
I2C_Config i2cCfg = {
#if 0
0x0000007f, /* I2COAR - Not used if master */
0x00000000, /* I2CIER - Disable interrupts, use polling */
0x0000001b, /* I2CCLKL - Low period for 100KHz operation */
0x0000001b, /* I2CCLKH - High period for 100KHz operation */
0x00000002, /* I2CCNT - Data words per transmission */
0x0000001a, /* I2CSAR - Slave address */
0x00004680, /* I2CMDR - Mode */
0x00000019 /* I2CPSC - Prescale 300MHz to 12MHz */
#else
0x0000007f, /* I2COAR - Not used if master */
0x00000000, /* I2CIER - Disable interrupts, use polling */
0x0000001b, /* I2CCLKL - Low period for 100KHz operation */
0x0000001b, /* I2CCLKH - High period for 100KHz operation */
0x00000000, /* I2CCNT - Data words per transmission */
0x0000001a, /* I2CSAR - Slave address aic23 i2c address*/
0x00004ea0, /* I2CMDR - Mode 4ea0*/
0x0000004a /* I2CPSC - Prescale 300MHz to 12MHz */
#endif
};
/************************************************************************/
/* (DEVSTAT) 0x01b3f004 -- Device Status Register */
/* (JTAGID) 0x01b3f008 -- JTAG Identification Register */
/* (PERCFG) 0x01b3f000 -- Peripheral Configuration Register */
/* (PCFGLOCK) 0x01b3f018 -- Peripheral Configuration Lock Register */
/************************************************************************/
EVMDM642_PCFGLOCK = 0x10c0010c; /* Unlock PERCFG through PCFGLOCK */
EVMDM642_PERCFG = 0x79; /* Enable VP0-VP2, I2C in PERCFG */
EVMDM642_wait(128); /* Wait at least 128 CPU cycles */
/* Restore settings for VPORT */
EVMDM642_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);/* Open I2C handle */
I2C_config(EVMDM642_I2C_hI2C, &i2cCfg); /* Configure I2C controller */
I2C_outOfReset(EVMDM642_I2C_hI2C); /* Take I2C out of reset */
}
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