memmap.h

S3C2440 base Wince USB_gadget driver

#include <s3c2440a_base_regs.h>
#include <s3c2440a_usbd.h>

/////
//(MCM2440A50\Src\Inc\oemaddrtab_cfg.inc, s3c2440a_base_regs.h)

//Address mapping (USB device controller register block)
#define	USBD_BASE_REG_PA			(S3C2440A_BASE_REG_PA_USBD)					//(0x52000000)   
#define USBD_BASE_REG_VA_CACHED		(0x91200000)
#define USED_BASE_REG_VA_UNCACHED	(USBD_BASE_REG_VA_CACHED + 0x20000000)		//(0xB1200000)

//Address mapping (I/O Port register block
#define	IOPORT_BASE_REG_PA			(S3C2440A_BASE_REG_PA_IOPORT)				//(0x56000000)            
#define	IOPORT_BASE_REG_VA_CACHED	(0x91600000) 
#define	IOPORT_BASE_REG_VA_UNCACHED	(IOPORT_BASE_REG_VA_CACHED + 0x20000000)	//(0xB1600000)
/////

#define USBD_BASE_REG_OFFSET		0x140
#define USBD_REGISTER_SET_SIZE		0x200


//Spec. offset - BASE_REG_OFFSET
#define SET_ADDRESS_REG_OFFSET		0x0
#define PWR_REG_OFFSET				0x4
#define EP_INT_REG_OFFSET			0x8
#define USB_INT_REG_OFFSET			0x18
#define EP_INT_EN_REG_OFFSET		0x1C
#define USB_INT_EN_REG_OFFSET		0x2C

#define EP0_FIFO_REG_OFFSET			0x80
#define EP1_FIFO_REG_OFFSET			0x84	//IN (DEVICE -> HOST)
#define EP2_FIFO_REG_OFFSET			0x88	//OUT(HOST -> DEVICE) 
#define EP3_FIFO_REG_OFFSET			0x8C
#define EP4_FIFO_REG_OFFSET			0x90

#define IDXADDR_REG_OFFSET          0x38

////
// Indexed Registers
//comon indexed register
#define MAX_PKT_SIZE_REG_OFFSET     0x40

//in indexed register
#define IN_CSR1_REG_OFFSET          0x44	
#define IN_CSR2_REG_OFFSET          0x48

//out indexed register
#define OUT_CSR1_REG_OFFSET         0x50
#define OUT_CSR2_REG_OFFSET         0x54
#define OUT_FIFO_CNT1_REG_OFFSET    0x58
#define OUT_FIFO_CNT2_REG_OFFSET    0x5C
////

// IN_CSR1_REG Bit definitions
#define IN_PACKET_READY             0x1
#define UNDER_RUN                   0x4   // Iso Mode Only
#define FLUSH_IN_FIFO               0x8
#define IN_SEND_STALL               0x10
#define IN_SENT_STALL               0x20
#define IN_CLR_DATA_TOGGLE          0x40

// Power Reg Bits
#define USB_RESET                   0x8
#define MCU_RESUME                  0x4
#define SUSPEND_MODE                0x2
#define SUSPEND_MODE_ENABLE_CTRL    0x1

// IN_CSR1_REG Bit definitions
#define IN_PACKET_READY             0x1
#define UNDER_RUN                   0x4   // Iso Mode Only
#define FLUSH_IN_FIFO               0x8
#define IN_SEND_STALL               0x10
#define IN_SENT_STALL               0x20
#define IN_CLR_DATA_TOGGLE          0x40

// EP0 CSR
#define EP0_OUT_PACKET_RDY          0x1
#define EP0_IN_PACKET_RDY           0x2
#define EP0_SENT_STALL              0x4
#define DATA_END                    0x8
#define SETUP_END                   0x10
#define EP0_SEND_STALL              0x20
#define SERVICED_OUT_PKY_RDY        0x40
#define SERVICED_SETUP_END          0x80

// OUT_CSR1_REG Bit definitions
#define OUT_PACKET_READY            0x1
#define FLUSH_OUT_FIFO              0x10
#define OUT_SEND_STALL              0x20
#define OUT_SENT_STALL              0x40
#define OUT_CLR_DATA_TOGGLE         0x80

// IN_CSR2_REG Bit definitions
#define IN_DMA_INT_DISABLE          0x10
#define SET_MODE_IN                 0x20 
#define SET_TYPE_ISO                0x40  // Note that Samsung does not currently support ISOCH 
#define AUTO_MODE                   0x80

// OUT_CSR2_REG Bit definitions
#define OUT_DMA_INT_DISABLE         0x10

// Can be used for Interrupt and Interrupt Enable Reg - common bit def
#define EP0_INT_INTR                0x1
#define EP1_INT_INTR                0x2
#define EP2_INT_INTR                0x4
#define EP3_INT_INTR                0x8
#define EP4_INT_INTR                0x10

#define CLEAR_ALL_EP_INTRS          (EP0_INT_INTR | EP1_INT_INTR | EP2_INT_INTR | EP3_INT_INTR | EP4_INT_INTR)

#define EP_INTERRUPT_DISABLE_ALL   0x0   // Bits to write to EP_INT_EN_REG - Use CLEAR

// Bit Definitions for USB_INT_REG and USB_INT_EN_REG_OFFSET
#define USB_RESET_INTR              0x4
#define USB_RESUME_INTR             0x2
#define USB_SUSPEND_INTR            0x1