lubbock.h

blob的完整代码

/*
 * lubbock.h: Lubbock specific defines
 */

#ifndef BLOB_ARCH_LUBBOCK_H
#define BLOB_ARCH_LUBBOCK_H

#include "blob/pxa.h"

/* the base address were BLOB is loaded by the first stage loader */
#define BLOB_ABS_BASE_ADDR	(0xA0000000)

/* where do various parts live in RAM */
#define BLOB_RAM_BASE		(0xA0100000)
#define KERNEL_RAM_BASE		(0xA0200000)
#define PARAM_RAM_BASE		(0xA0180000)
#define RAMDISK_RAM_BASE	(0xA0400000)

/* FIXME : Param/Ramdisk is not supported */

/* and where do they live in flash */
#define BLOB_FLASH_BASE		(0x00000000)
//#define BLOB_FLASH_LEN	(256 * 1024)
#define BLOB_FLASH_LEN		(128 * 1024)	//zwj
#define PARAM_FLASH_BASE	(BLOB_FLASH_BASE + BLOB_FLASH_LEN)
// #define PARAM_FLASH_LEN	(256 * 1024)
#define PARAM_FLASH_LEN		(0)
//#define KERNEL_FLASH_BASE	(PARAM_FLASH_BASE + PARAM_FLASH_LEN)
//#define KERNEL_FLASH_BASE	(0x40000)
#define KERNEL_FLASH_BASE	(0x20000)	//zwj
//#define KERNEL_FLASH_LEN	(1024 * 1024)
#define KERNEL_FLASH_LEN	(640 * 1024)	//zwj
#define RAMDISK_FLASH_BASE	(KERNEL_FLASH_BASE + KERNEL_FLASH_LEN)
#define RAMDISK_FLASH_LEN	(4 * 1024 * 1024)


/* the position of the kernel boot parameters */
#define BOOT_PARAMS		(0xA0000100)


/* the size (in kbytes) to which the compressed ramdisk expands */
#define RAMDISK_SIZE		(8 * 1024)


/* CPU specific Area */

#define MEMC_BASE	0x48000000
#define SDRAM_BASE	0xA0000000
#define OSCR_BASE	0x40A00010
#define FPGA_REGS_BASE	0x08000000

#define MDCNFG_OFFSET	0x00
#define MDREFR_OFFSET	0x04
#define MSC0_OFFSET	0x08
#define MSC1_OFFSET	0x0C
#define MSC2_OFFSET	0x10
#define MECR_OFFSET	0x14
#define SXLCR_OFFSET	0x18
#define SXCNFG_OFFSET	0x1C
#define FLYCNFG_OFFSET	0x20
#define SXMRS_OFFSET	0x24
#define MCMEM0_OFFSET	0x28
#define MCMEM1_OFFSET	0x2C
#define MCATT0_OFFSET	0x30
#define MCATT1_OFFSET	0x34
#define MCIO0_OFFSET	0x38
#define MCIO1_OFFSET	0x3C
#define MDMRS_OFFSET	0x40
#define BOOT_DEF_OFFSET 0x44

#if ( defined(CPU_pxa250) || defined(CPU_pxa255) || defined(pxa255)) 

/* FPGA */
#define __LUB_REG(x)	(*(volatile unsigned long*)(x))
#define WHOAMI_OFFSET		0x00
#define HEX_LED_OFFSET		0x10
#define LED_BLANK_OFFSET 	0x40
#define CNFG_SW_OFFSET		0x50
#define USER_SW_OFFSET		0x60
#define MISC_WR_OFFSET		0x80

/* SDRAM */
//#define MDCNFG_VAL	0x00001AC9		//czhou
//#define MDCNFG_VAL	0x00001A4B		//czhou
//#define MDCNFG_VAL	0x00000AC9		//czhou
#define MDCNFG_VAL	0x00000AA9		//czhou
#define MDREFR_VAL	0x00018018 
#define MDMRS_VAL	0x00000000

/* Static Memory */
//#define MSC0_VAL	0x23F223F2
//#define MSC0_VAL	0x23D223D2		//czhou
#define MSC0_VAL	0x23F223FA		//czhou
#define MSC1_VAL	0x3FF1A441
#define MSC2_VAL	0x7FF17FF1

#elif (defined(CPU_pxa262) )  /* Dalhart B0 */

/* FPGA */
#define __LUB_REG(x)	(*(volatile unsigned long*)(x))
#define WHOAMI_OFFSET		0x00
#define HEX_LED_OFFSET		0x10
#define LED_BLANK_OFFSET 	0x40
#define CNFG_SW_OFFSET		0x50
#define USER_SW_OFFSET		0x60
#define MISC_WR_OFFSET		0x80

/* SDRAM */
#define MDCNFG_VAL	0x00001AC9
#define MDREFR_VAL	0x00018018 
#define MDMRS_VAL	0x00000000

/* Static Memory */
#define MSC0_VAL	0x24FA24FA
#define MSC1_VAL	0x3FF1A441
#define MSC2_VAL	0x7FF17FF1

#endif

/* GPIO settings */
#define GPSR0_VAL 	0x00008000	//GPSR OUTPUT SET REGISTER
//#define GPSR1_VAL	0x00000384
#define GPSR1_VAL	0x00008182	//czhou
#define GPSR2_VAL	0x0001c000

#define GPCR0_VAL	0x00000000	//GPCR OUTPUT CLEAN REGISTER
#define GPCR1_VAL	0x00000000
#define GPCR2_VAL	0x00000000

#define GPDR0_VAL	0x00008000	//GPDR direction register
//#define GPDR1_VAL	0x00000380
#define GPDR1_VAL	0x00008182	//czhou
#define GPDR2_VAL	0x0001c000

/*
15	10	NCS1
33	10	NCS5
34	01	FFRXD
39	10	FFTXD
40	10	FFDTR
41	10	FFRTS
46	10	STRXD
47	01	STTXD
78	10	NCS2
79	10	NCS3
80	10	NCS4
*/
#define GAFR0_L_VAL	0x80000000	//GAFR alternate function
#define GAFR0_U_VAL	0x00000000
//#define GAFR1_L_VAL	0x000a8010	//czhou
#define GAFR1_L_VAL	0x600a8018	//czhou
#define GAFR1_U_VAL	0x00000000
#define GAFR2_L_VAL	0xa0000000
#define GAFR2_U_VAL	0x00000002

/* PCMCIA and CF Interfaces */
#define MECR_VAL	0x00000000
#define MCMEM0_VAL	0x00010504
#define MCMEM1_VAL	0x00010504
#define MCATT0_VAL	0x00010504
#define MCATT1_VAL	0x00010504
#define MCIO0_VAL	0x00004715
#define MCIO1_VAL	0x00004715
/* Sync Static Memory */
#define SXCNFG_VAL	0x00000000
#define SXMRS_VAL	0x00000000	/* NOT USED */
#define SXLCR_VAL	0x00000000	/* NOT USED */
#define FLYCNFG_VAL	0x01FE01FE	/* NOT USED */


#define WHOAMI		__LUB_REG(FPGA_REGS_BASE+ WHOAMI_OFFSET)
#define HEX_LED 	__LUB_REG(FPGA_REGS_BASE+ HEX_LED_OFFSET)
#define LED_BLANK 	__LUB_REG(FPGA_REGS_BASE + LED_BLANK_OFFSET)
#define CNFG_SW		__LUB_REG(FPGA_REGS_BASE + CFNG_SW_OFFSET)
#define USER_SW		__LUB_REG(FPGA_REGS_BASE + USER_SW_OFFSET)
#define MISC_WR		__LUB_REG(FPGA_REGS_BASE + MISC_WR_OFFSET)

#endif