📄 startup.s
字号:
OPT 2
INCLUDE kxarm.h
INCLUDE option.inc
INCLUDE s2440addr.inc
INCLUDE memcfg.inc
OPT 1
OPT 128
; Pre-defined constants.
;
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
; Stack locations.
;
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ; 0x33ff5800 ~
UserStack EQU (_STACK_BASEADDRESS-0x3800) ; 0x33ff4800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ; 0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ; 0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ; 0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ; 0x33ff8000 ~
;------------------------------------------------------------------------------
; Sleep state constants
;
; Location of sleep data
; BUGBUG - this needs to be declared as a local var.
SLEEPDATA_BASE_PHYSICAL EQU 0x30028000
WORD_SIZE EQU 0x4
; Sleep State memory locations
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start + 0)
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE)
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE)
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE)
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE)
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE)
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE)
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE)
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE)
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE)
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE)
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE)
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE)
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE)
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE)
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE)
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE)
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE)
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE)
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE)
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE)
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE)
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE)
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE)
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE)
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE)
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
; for S3C2440 v0.19 board
; 300MHz -> 1.1 +- 0.05 Volt
; 400MHz -> 1.2 +- 0.05 Volt
; 533MHz -> 1.35 +- 0.05 Volt
; /////////////////////////////////////////
; // D4 D3 D2 D1 D0
; // 0 0 1 1 1 // 1.40V/
; // 0 1 0 0 0 // 1.35V/
; // 0 1 0 0 1 // 1.30V
; // 0 1 0 1 0 // 1.25V
; // 0 1 0 1 1 // 1.20V
; // 0 1 1 0 0 // 1.15V
; // 0 1 1 0 1 // 1.10V
; // 0 1 1 1 0 // 1.05V
; // 0 1 1 1 1 // 1.00V
; // 1 0 0 0 1 // 0.95V
; // 1 0 0 1 1 // 0.90V
; // 1 0 1 0 1 // 0.85V
; // 1 0 1 1 1 // 0.80V
GBLA CLKVAL
;CLKVAL SETA 266
;CLKVAL SETA 296
CLKVAL SETA 399
;CLKVAL SETA 315
;CLKVAL SETA 399
;CLKVAL SETA 406
;CLKVAL SETA 530
[ CLKVAL = 406
FCLK EQU (406)
PLLVAL EQU (((64 << 12) + (4 << 4) + 0))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.2 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 1
D0VAL EQU 1
]
[ CLKVAL = 296
FCLK EQU (296)
PLLVAL EQU (((97 << 12) + (1 << 4) + 2))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
[ CLKVAL = 299
FCLK EQU (299)
PLLVAL EQU (((116 << 12) + (5 << 4) + 1))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
[ CLKVAL = 266
FCLK EQU (266)
PLLVAL EQU (((118 << 12) + (2 << 4) + 2))
CLKDIVVAL EQU 3 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.05 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
[ CLKVAL = 315
FCLK EQU (315)
PLLVAL EQU (((85 << 12) + (3 << 4) + 1))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.05 V
D3VAL EQU 1
D2VAL EQU 1
D1VAL EQU 1
D0VAL EQU 0
]
[ CLKVAL = 399
FCLK EQU (399)
PLLVAL EQU (((110 << 12) + (3 << 4) + 1))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.3V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 1
]
[ CLKVAL = 530
FCLK EQU (530)
PLLVAL EQU (((86 << 12) + (1 << 4) + 1))
CLKDIVVAL EQU 5 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
UPLLVAL EQU (((60 << 12) + (0x4 << 4) + 0x2)) ;48MHz
;---------------------------------------------------------------------------
; Voltage Change function
; The LEDs are located below AMD Flash ROM
MACRO
VOLTAGECHANGE
ldr r8, = GPBDAT ; D4
ldr r9, [r8]
ldr r10, = 0x77f
and r9, r9, r10
ldr r10, = (D4VAL<<7)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPFDAT ; D3~0
ldr r9, [r8]
ldr r10, = 0x0f
and r9, r9, r10
ldr r10, = ((D3VAL<<7)+(D2VAL<<6)+(D1VAL<<5)+(D0VAL<<4))
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB7: Output
ldr r9, [r8]
ldr r10, = 0x3f3fff
and r9, r9, r10
ldr r10, = (1<<14)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPFCON ; GPF4~7: Output
ldr r9, [r8]
ldr r10, = 0x00ff
and r9, r9, r10
ldr r10, = 0x5500
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Latch enable
ldr r9, [r8]
ldr r10, = ~(0<<8)
and r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB8: Output
ldr r9, [r8]
ldr r10, = 0x3cffff
and r9, r9, r10
ldr r10, = (1<<16)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Output enable
ldr r9, [r8]
ldr r10, = (1<<10)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB10: Output
ldr r9, [r8]
ldr r10, = 0x0fffff
and r9, r9, r10
ldr r10, = (1<<20)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Latch disable
ldr r9, [r8]
ldr r10, = (1<<8)
orr r9, r9, r10
str r9, [r8]
MEND
;---------------------------------------------------------------------------
IMPORT main ; C entrypoint for Steppingstone loader.
EXPORT MMU_EnableICache
EXPORT MMU_SetAsyncBusMode
STARTUPTEXT
LEAF_ENTRY StartUp
b ResetHandler
b .
b .
b .
b .
b .
b .
b .
PowerOffCPU
str r1, [r0] ; Enable SDRAM self-refresh
str r3, [r2] ; MISCCR Setting
str r5, [r4] ; Power Off !!
b .
; Resume handler code.
;
WAKEUP_POWER_OFF
; Release SCLKn after wake-up from the POWER_OFF mode.
ldr r1, =MISCCR
ldr r0, [r1]
bic r0, r0, #(7<<17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H.
str r0, [r1]
; Set up the memory control registers.
;
add r0, pc, #SMRDATA - (. + 8)
ldr r1, =BWSCON ; BWSCON Address.
add r2, r0, #52 ; End address of SMRDATA.
3
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B3
mov r0, #0x2000
4
subs r0, r0, #1
bne %B4
;------------------------------------------------------------------------------
; Recover Process : Starting Point
;
; 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 ; pointer for checksum calculation
ldr r2, =0x0
ldr r0, =(SLEEPDATA_SIZE-1) ; get size of data structure to do checksum on
50
ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, ROR #31
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