📄 gsm_ddc_cic.mdl
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SourceBlock "xbsIndex_r4/Relational"
SourceType "Xilinx Arithmetic Relational Operator Block"
mode "a=b"
en "off"
latency "1"
dbl_ovrd "off"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,20,348,193"
block_type "relational"
block_version "10.1"
sg_icon_stat "55,56,1,1,white,blue,0,1cf02e61,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 "
"32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 "
"50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56"
" 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be"
"gin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a=b}\\newlinez^"
"{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "mux_en"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Scope
Name "Scope"
Ports [9]
Position [1060, 835, 1120, 975]
Floating off
Location [1640, 50, 2548, 859]
Open off
NumInputPorts "9"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
axes4 "%<SignalLabel>"
axes5 "%<SignalLabel>"
axes6 "%<SignalLabel>"
axes7 "%<SignalLabel>"
axes8 "%<SignalLabel>"
axes9 "%<SignalLabel>"
}
TimeRange "10000"
YMin "0~0~0~0~0~0~-0.2~-0.2~0"
YMax "300~4~1.2~1.2~40~1.2~0.2~0.2~1"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
SampleTime "0"
}
Block {
BlockType Reference
Name "Slice1"
Ports [1, 1]
Position [550, 580, 610, 610]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each in"
"put sample and presents it at the output. The output type is ordinarily unsi"
"gned with binary point at zero, but can be Boolean when the slice is one bit "
"wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "2"
boolean_output "off"
mode "Upper Bit Location + Width"
bit1 "-1"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,376"
block_type "slice"
block_version "10.1"
sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 3"
"0 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20"
" 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 "
"30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg"
"in icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','"
"COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "ram_addr"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Slice2"
Ports [1, 1]
Position [550, 730, 610, 760]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each in"
"put sample and presents it at the output. The output type is ordinarily unsi"
"gned with binary point at zero, but can be Boolean when the slice is one bit "
"wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "5"
boolean_output "off"
mode "Upper Bit Location + Width"
bit1 "-4"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,376"
block_type "slice"
block_version "10.1"
sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 3"
"0 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20"
" 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 "
"30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg"
"in icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','"
"COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "mux_sample"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Slice3"
Ports [1, 1]
Position [550, 625, 610, 655]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each in"
"put sample and presents it at the output. The output type is ordinarily unsi"
"gned with binary point at zero, but can be Boolean when the slice is one bit "
"wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "1"
boolean_output "off"
mode "Upper Bit Location + Width"
bit1 "-3"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,376"
block_type "slice"
block_version "10.1"
sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 3"
"0 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20"
" 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 "
"30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg"
"in icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','"
"COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "mux_sel"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Slice4"
Ports [1, 1]
Position [550, 530, 610, 560]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each in"
"put sample and presents it at the output. The output type is ordinarily unsi"
"gned with binary point at zero, but can be Boolean when the slice is one bit "
"wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "1"
boolean_output "off"
mode "Upper Bit Location + Width"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,376"
block_type "slice"
block_version "10.1"
sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 3"
"0 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20"
" 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 "
"30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg"
"in icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','"
"COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Slice5"
Ports [1, 1]
Position [550, 680, 610, 710]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each in"
"put sample and presents it at the output. The output type is ordinarily unsi"
"gned with binary point at zero, but can be Boolean when the slice is one bit "
"wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "1"
boolean_output "off"
mode "Upper Bit Location + Width"
bit1 "-4"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,376"
block_type "slice"
block_version "10.1"
sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 3"
"0 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20"
" 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 "
"30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg"
"in icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','"
"COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "count_vout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Terminator
Name "T1"
Position [240, 152, 255, 168]
}
Block {
BlockType Terminator
Name "T2"
Position [240, 287, 255, 303]
}
Block {
BlockType Terminator
Name "T3"
Position [240, 72, 255, 88]
}
Block {
BlockType Terminator
Name "T7"
Position [940, 153, 955, 167]
}
Block {
BlockType Terminator
Name "T8"
Position [240, 367, 255, 383]
}
Block {
BlockType Terminator
Name "T9"
Position [940, 343, 955, 357]
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [465, 49, 540, 81]
VariableName "sg_ycic_norm"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ToWorkspace
Name "To Workspace1"
Position [985, 758, 1080, 792]
VariableName "cic_dout_strobes"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType Reference
Name "cic_i_dec64_1v1"
Ports [2, 5]
Position [135, 25, 215, 215]
SourceBlock "xbsIndex_r4/CIC Compiler 1.1 "
SourceType "Xilinx CIC Compiler 1.1 Block"
infoedit "Provides the ability to design and implemen"
"t Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices"
".<P><P>Hardware notes: Optional mapping to DSP48/E/A primitives."
filter_type "Decimation"
number_of_stages "5"
differential_delay "1"
number_of_channels "4"
input_data_width "17"
output_data_width "17"
sample_rate_changes "Fixed"
fixed_or_initial_rate "64"
minimum_rate "4"
maximum_rate "4"
ce "off"
sclr "off"
use_xtreme_dsp_slice "off"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
ip_name "CIC Compiler"
ip_version "1.1"
dsptool_ready "true"
structural_sim "true"
has_advanced_control "0"
sggui_pos "20,20,348,694"
block_type "cic_compiler_v1_0"
block_version "10.1"
sg_icon_stat "80,190,1,1,white,blue,0,5d81e486,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');"
"\ncolor('black');port_label('input',2,'nd');\ncolor('black');port_label('outp"
"ut',1,'dout');\ncolor('black');port_label('output',2,'rfd');\ncolor('black');"
"port_label('output',3,'rdy');\ncolor('black');port_label('output',4,'chan_syn"
"c');\ncolor('black');port_label('output',5,'chan_out');\nfprintf('','COMMENT:"
" end icon text');\n"
Port {
PortNumber 3
Name "count_rst"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "cic_q_dec64_1v1"
Ports [2, 5]
Position [135, 240, 215, 430]
SourceBlock "xbsIndex_r4/CIC Compiler 1.1 "
SourceType "Xilinx CIC Compiler 1.1 Block"
infoedit "Provides the ability to design and implemen"
"t Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices"
".<P><P>Hardware notes: Optional mapping to DSP48/E/A primitives."
filter_type "Decimation"
number_of_stages "5"
differential_delay "1"
number_of_channels "4"
input_data_width "17"
output_data_width "17"
sample_rate_changes "Fixed"
fixed_or_initial_rate "64"
minimum_rate "4"
maximum_rate "4"
ce "off"
sclr "off"
use_xtreme_dsp_slice "off"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
ip_name "CIC Compiler"
ip_version "1.1"
dsptool_ready "true"
structural_sim "true"
has_advanced_control "0"
sggui_pos "20,20,348,694"
block_type "cic_compiler_v1_0"
block_version "10.1"
sg_icon_stat "80,190,1,1,white,blue,0,5d81e486,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');"
"\ncolor('black');port_label('input',2,'nd');\ncolor('black');port_label('outp"
"ut',1,'dout');\ncolor('black');port_label('output',2,'rfd');\ncolor('black');"
"port_label('output',3,'rdy');\ncolor('black');port_label('output',4,'chan_syn"
"c');\ncolor('black');port_label('output',5,'chan_out');\nfprintf('','COMMENT:"
" end icon text');\n"
Port {
PortNumber 1
Name "cic_dout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "ignore1"
Ports [1, 1]
Position [370, 450, 430, 470]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed p"
"oint inputs into ouputs of type Simulink integer, double, or fixed point.<P><"
"P>Hardware notes: In hardware these blocks become top level output ports or "
"are discarded, depending on how they are configured."
hdl_port "on"
timing_constraint "None"
locs_specified "off"
LOCs "{}"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
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