📄 ddc_dds_capture.mdl
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"evices or technologies is expressly prohibited and immediately terminates you"
"r license
\nunless covered by a separate agreement.<br>
\n<br>
\nXilinx is p"
"roviding this design, code, or information \"as-is\" solely for use in develo"
"ping programs and
\nsolutions for Xilinx devices, with no obligation on the "
"part of Xilinx to provide support. By providing
\nthis design, code, or infor"
"mation as one possible implementation of this feature, application or standar"
"d,
\nXilinx is making no representation that this implementation is free from"
" any claims of infringement. You
\nare responsible for obtaining any rights y"
"ou may require for your implementation. Xilinx expressly disclaims
\nany warr"
"anty whatsoever with respect to the adequacy of the implementation, including"
" but not limited to any
\nwarranties or representations that this implementat"
"ion is free from claims of infringement, implied warranties
\nof merchantabil"
"ity or fitness for a particular purpose.<br>
\n<br>
\nXilinx products are not"
" intended for use in life support appliances, devices, or systems. Use in suc"
"h
\napplications is expressly prohibited.<br>
\n<br>
\nAny modifications tha"
"t are made to the Source Code are done at the user's sole risk and will be un"
"supported.<br>
\n<br>
\nThis copyright and support notice must be retained as"
" part of this text at all times.
\n(c) Copyright 1995-2008 Xilinx, Inc. All "
"rights reserved.
\n "
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "copyright"
block_version "10.1.3"
sg_icon_stat "199,98,-1,-1,beige,white,0,07734,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 199 199 0 ],[0 0 98 98 ],[0.98 0.96 0.92]);\npatch([73 57 80 57 73 99 "
"106 113 141 119 98 83 106 83 98 119 141 113 106 99 73 ],[11 27 50 73 89 89 82"
" 89 89 67 88 73 50 27 12 33 11 11 18 11 11 ],[0.93 0.92 0.86]);\nplot([0 199 "
"199 0 0 ],[0 0 98 98 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprint"
"f('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\ndis"
"p('{\\fontsize{12pt}(c) Copyright 1995-2008 Xilinx, Inc.}\\newline \\newline "
"','texmode','on');\ndisp('{\\fontsize{12pt}#-- All rights reserved.}','texmod"
"e','on');\ndisp('\\newline \\newline \\newline \\newline \\newline \\newline{"
"\\fontsize{12pt}Double Click for Copyright Notice}','texmode','on');\n"
}
Block {
BlockType Reference
Name "DDS Compiler v2_0 "
Ports [3, 3]
Position [360, 88, 440, 192]
SourceBlock "xbsIndex_r4/DDS Compiler v2_0 "
SourceType "Xilinx DDS Compiler v2_0 Block"
dds_clock_rate "(1.625/5)*8*2*16*4"
sfdr "115"
frequency_resolution "0.1"
mode "Sine and Cosine"
neg_sin on
neg_cos off
channels "4"
output_frequency_type "Programmable"
output_frequency_array "[ 0.3 0.9 1.5 2.1 ]"
phase_offset_type "None"
phase_offset_array "[0.0]"
explicit_period "on"
period "1"
noise_shaping "Taylor series corrected"
channel_port on
RFD off
RDY off
rst off
en off
dbl_ovrd off
mem_type "Block RAM"
dsp48_use "Maximal"
latency_configuration "Auto"
latency "1"
accum_latency "One Cycle"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
version "1"
acc_latency "2"
has_advanced_control "0"
sggui_pos "20,20,348,623"
block_type "dds_compilerv20"
block_version "10.1"
sg_icon_stat "80,104,3,3,white,blue,0,66a57b48,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 3"
"8 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 4"
"5 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 "
"0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin "
"icon text');\ncolor('black');port_label('input',1,'channelsel');\ncolor('blac"
"k');port_label('input',2,'data');\ncolor('black');port_label('input',3,'we');"
"\ncolor('black');port_label('output',1,'-sin');\ncolor('black');port_label('o"
"utput',2,'cos');\ncolor('black');port_label('output',3,'channel');\nfprintf('"
"','COMMENT: end icon text');\n"
Port {
PortNumber 1
Name "dds_sin"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 2
Name "dds_cos"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 3
Name "dds_channel"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Mux
Name "Mux"
Ports [3, 1]
Position [595, 111, 600, 169]
ShowName off
Inputs "3"
DisplayOption "bar"
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [665, 125, 725, 155]
VariableName "ddc_dds_out"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType SubSystem
Name "freq_progam"
Ports [0, 3]
Position [140, 100, 195, 180]
BackgroundColor "[1.000000, 0.756863, 0.756863]"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskType "DDS Freq. Programming Stimulus"
MaskDescription "This block writes the desired mixing freqencies"
" into the programmable frequency port of the DDS."
MaskPromptString "Frequency Vector (MHz)|Sample Freq (MHz)"
MaskStyleString "edit,edit"
MaskTunableValueString "off,off"
MaskCallbackString "|"
MaskEnableString "on,on"
MaskVisibilityString "on,on"
MaskToolTipString "on,on"
MaskVarAliasString ","
MaskVariables "FREQ_VEC=@1;Fc=@2;"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "carriers.'/1e6|fs_dds/1e6"
MaskTabNameString ","
System {
Name "freq_progam"
Location [271, 329, 1585, 1166]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType SubSystem
Name "wen"
Ports [0, 1]
Position [25, 96, 70, 114]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "wen"
Location [219, 389, 885, 587]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Constant
Name "Constant"
Position [25, 41, 45, 59]
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [150, 30, 205, 70]
OutFrame "Frame based"
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn"
Position [65, 35, 125, 65]
MATLABFcn "[ 0 0 0 ones(1,length(FREQ_VEC)) zeros("
"1,10000) ]"
Output1D off
}
Block {
BlockType Reshape
Name "Reshape1"
Position [225, 36, 255, 64]
OutputDimensionality "Column vector (2-D)"
}
Block {
BlockType Reference
Name "Unbuffer"
Ports [1, 1]
Position [275, 28, 325, 72]
SourceBlock "dspbuff3/Unbuffer"
SourceType "Unbuffer"
ic "0"
}
Block {
BlockType Outport
Name "Out"
Position [430, 43, 460, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Unbuffer"
SrcPort 1
DstBlock "Out"
DstPort 1
}
Line {
SrcBlock "Frame Conversion"
SrcPort 1
DstBlock "Reshape1"
DstPort 1
}
Line {
SrcBlock "Reshape1"
SrcPort 1
DstBlock "Unbuffer"
DstPort 1
}
Line {
Labels [0, 0]
SrcBlock "MATLAB Fcn"
SrcPort 1
DstBlock "Frame Conversion"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "MATLAB Fcn"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "wr_chn"
Ports [0, 1]
Position [25, 26, 70, 44]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "wr_chn"
Location [255, 708, 921, 906]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Constant
Name "Constant"
Position [25, 41, 45, 59]
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [150, 30, 205, 70]
OutFrame "Frame based"
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn"
Position [65, 35, 125, 65]
MATLABFcn "[ 0 0 0 0 1:length(FREQ_VEC)-1 zeros(1,"
"10000) ]"
Output1D off
}
Block {
BlockType Reshape
Name "Reshape1"
Position [225, 36, 255, 64]
OutputDimensionality "Column vector (2-D)"
}
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