📄 gsm_duc_cic.mdl
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Line {
SrcBlock "Demux"
SrcPort 16
Points [0, 10]
DstBlock "Mux"
DstPort 8
}
Line {
SrcBlock "Demux"
SrcPort 15
Points [0, 10]
DstBlock "Mux"
DstPort 7
}
Line {
SrcBlock "Demux"
SrcPort 14
Points [0, 10]
DstBlock "Mux"
DstPort 6
}
Line {
SrcBlock "Demux"
SrcPort 13
Points [0, 10]
DstBlock "Mux"
DstPort 5
}
Line {
SrcBlock "Demux"
SrcPort 12
Points [0, 10]
DstBlock "Mux"
DstPort 4
}
Line {
SrcBlock "Demux"
SrcPort 11
Points [0, 10]
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "Demux"
SrcPort 10
Points [0, 10]
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Demux"
SrcPort 9
Points [0, 10]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
DstBlock "c1_i"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "c1_q"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 3
DstBlock "c2_i"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 4
DstBlock "c2_q"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 5
DstBlock "c3_i"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 6
DstBlock "c3_q"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 7
DstBlock "c4_i"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 8
DstBlock "c4_q"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "CIC"
Ports [3, 4]
Position [950, 224, 1040, 411]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "CIC"
Location [63, 110, 1566, 1101]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "din_i"
Position [65, 93, 95, 107]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "din_q"
Position [70, 398, 100, 412]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "vin"
Position [65, 228, 95, 242]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "Scale"
Ports [1, 1]
Position [375, 27, 430, 83]
SourceBlock "xbsIndex_r4/Scale"
SourceType "Xilinx Input Scaler Block"
infoedit "Scales input by a power of two by adjusting"
" the binary point position.<P><P>Hardware notes: In hardware this block costs"
" nothing."
scale_factor "-1*log2(gain(hcic_duc))"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,336,191"
block_type "scale"
block_version "10.1"
sg_icon_stat "55,56,1,1,white,blue,0,5b20091b,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 "
"32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 "
"50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56"
" 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be"
"gin icon text');\ncolor('black');disp('\\bf{2^{-12}}','texmode','on');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Scale1"
Ports [1, 1]
Position [375, 332, 430, 388]
SourceBlock "xbsIndex_r4/Scale"
SourceType "Xilinx Input Scaler Block"
infoedit "Scales input by a power of two by adjusting"
" the binary point position.<P><P>Hardware notes: In hardware this block costs"
" nothing."
scale_factor "-1*log2(gain(hcic_duc))"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,336,191"
block_type "scale"
block_version "10.1"
sg_icon_stat "55,56,1,1,white,blue,0,5b20091b,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 "
"32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 "
"50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56"
" 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be"
"gin icon text');\ncolor('black');disp('\\bf{2^{-12}}','texmode','on');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Terminator
Name "T1"
Position [465, 210, 480, 230]
}
Block {
BlockType Terminator
Name "T2"
Position [380, 515, 395, 535]
}
Block {
BlockType Terminator
Name "T3"
Position [375, 100, 390, 120]
}
Block {
BlockType Terminator
Name "T6"
Position [380, 405, 395, 425]
}
Block {
BlockType Reference
Name "cic_i_int16x_1v1 "
Ports [2, 5]
Position [200, 31, 310, 299]
SourceBlock "xbsIndex_r4/CIC Compiler 1.1 "
SourceType "Xilinx CIC Compiler 1.1 Block"
infoedit "Provides the ability to design and implemen"
"t Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices"
".<P><P>Hardware notes: Optional mapping to DSP48/E/A primitives."
filter_type "Interpolation"
number_of_stages "4"
differential_delay "1"
number_of_channels "4"
input_data_width "18"
output_data_width "18"
sample_rate_changes "Fixed"
fixed_or_initial_rate "m_cic"
minimum_rate "4"
maximum_rate "4"
ce "off"
sclr "off"
use_xtreme_dsp_slice "off"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
ip_name "CIC Compiler"
ip_version "1.1"
dsptool_ready "true"
structural_sim "true"
has_advanced_control "0"
sggui_pos "20,20,348,694"
block_type "cic_compiler_v1_0"
block_version "10.1"
sg_icon_stat "110,268,1,1,white,blue,0,5d81e486,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');"
"\ncolor('black');port_label('input',2,'nd');\ncolor('black');port_label('outp"
"ut',1,'dout');\ncolor('black');port_label('output',2,'rfd');\ncolor('black');"
"port_label('output',3,'rdy');\ncolor('black');port_label('output',4,'chan_syn"
"c');\ncolor('black');port_label('output',5,'chan_out');\nfprintf('','COMMENT:"
" end icon text');\n"
Port {
PortNumber 1
Name "cic_i_dout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 2
Name "cic_i_rfd"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 3
Name "cic_i_vout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 4
Name "cic_i_sync"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 5
Name "cic_i_ch_out"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "cic_q_int16x_1v1"
Ports [2, 5]
Position [200, 336, 310, 604]
SourceBlock "xbsIndex_r4/CIC Compiler 1.1 "
SourceType "Xilinx CIC Compiler 1.1 Block"
infoedit "Provides the ability to design and implemen"
"t Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices"
".<P><P>Hardware notes: Optional mapping to DSP48/E/A primitives."
filter_type "Interpolation"
number_of_stages "4"
differential_delay "1"
number_of_channels "4"
input_data_width "18"
output_data_width "18"
sample_rate_changes "Fixed"
fixed_or_initial_rate "m_cic"
minimum_rate "4"
maximum_rate "4"
ce "off"
sclr "off"
use_xtreme_dsp_slice "off"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
ip_name "CIC Compiler"
ip_version "1.1"
dsptool_ready "true"
structural_sim "true"
has_advanced_control "0"
sggui_pos "20,20,348,694"
block_type "cic_compiler_v1_0"
block_version "10.1"
sg_icon_stat "110,268,1,1,white,blue,0,5d81e486,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');"
"\ncolor('black');port_label('input',2,'nd');\ncolor('black');port_label('outp"
"ut',1,'dout');\ncolor('black');port_label('output',2,'rfd');\ncolor('black');"
"port_label('output',3,'rdy');\ncolor('black');port_label('output',4,'chan_syn"
"c');\ncolor('black');port_label('output',5,'chan_out');\nfprintf('','COMMENT:"
" end icon text');\n"
Port {
PortNumber 1
Name "cic_q_dout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 2
Name "cic_q_rfd"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 3
Name "cic_q_vout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 4
Name "cic_q_sync"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 5
Name "cic_q_ch_out"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "ignore1"
Ports [1, 1]
Position [430, 460, 490, 480]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed p"
"oint inputs into ouputs of type Simulink integer, double, or fixed point.<P><"
"P>Hardware notes: In hardware these blocks become top level output ports or "
"are discarded, depending on how they are configured."
hdl_port "on"
timing_constraint "None"
locs_specified "off"
LOCs "{}"
xl_use_area "off"
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
block_version "10.1"
sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 2"
"9 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14"
" 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 2"
"0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi"
"n icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "ignore2"
Ports [1, 1]
Position [405, 570, 465, 590]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed p"
"oint inputs into ouputs of type Simulink integer, double, or fixed point.<P><"
"P>Hardware notes: In hardware these blocks become top level output ports or "
"are discarded, depending on how they are configured."
hdl_port "on"
timing_constraint "None"
locs_specified "off"
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