📄 duc_dds_capture.mdl
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SourceType "Unbuffer"
ic "0"
}
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BlockType Outport
Name "Out"
Position [430, 43, 460, 57]
IconDisplay "Port number"
BusOutputAsStruct off
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Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "MATLAB Fcn"
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Line {
Labels [0, 0]
SrcBlock "MATLAB Fcn"
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DstBlock "Frame Conversion"
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SrcBlock "Reshape1"
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BlockType SubSystem
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RTWSystemCode "Auto"
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System {
Name "wr_data"
Location [899, 762, 1565, 960]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
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ZoomFactor "100"
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BlockType Constant
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VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
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Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [150, 30, 205, 70]
OutFrame "Frame based"
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Block {
BlockType MATLABFcn
Name "MATLAB Fcn"
Position [65, 35, 125, 65]
MATLABFcn "[ 0 0 0 FREQ_VEC zeros(1,10000) ]./Fc"
Output1D off
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Block {
BlockType Reshape
Name "Reshape1"
Position [225, 36, 255, 64]
OutputDimensionality "Column vector (2-D)"
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Block {
BlockType Reference
Name "Unbuffer"
Ports [1, 1]
Position [275, 28, 325, 72]
SourceBlock "dspbuff3/Unbuffer"
SourceType "Unbuffer"
ic "0"
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BlockType Outport
Name "Out"
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IconDisplay "Port number"
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SrcBlock "Reshape1"
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SrcBlock "MATLAB Fcn"
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DstBlock "Frame Conversion"
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SrcBlock "Constant"
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DstBlock "MATLAB Fcn"
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BlockType Outport
Name "wr_ch"
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IconDisplay "Port number"
BusOutputAsStruct off
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BlockType Outport
Name "wdata"
Position [135, 63, 165, 77]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
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Block {
BlockType Outport
Name "we"
Position [135, 98, 165, 112]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
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Line {
SrcBlock "wr_chn"
SrcPort 1
DstBlock "wr_ch"
DstPort 1
}
Line {
SrcBlock "wr_data"
SrcPort 1
DstBlock "wdata"
DstPort 1
}
Line {
SrcBlock "wen"
SrcPort 1
DstBlock "we"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "wdata"
Ports [1, 1]
Position [225, 131, 270, 149]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "32"
bin_pt "32"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,20,356,423"
block_type "gatewayin"
block_version "9.1.01"
sg_icon_stat "45,18,1,1,white,yellow,0,bc55d28f,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33"
" 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 "
"15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','t"
"exmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMME"
"NT: end icon text');\n"
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PortNumber 1
Name "wdata"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
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BlockType Reference
Name "we"
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SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Boolean"
n_bits "18"
bin_pt "17"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,20,356,423"
block_type "gatewayin"
block_version "9.1.01"
sg_icon_stat "45,18,1,1,white,yellow,0,bc55d28f,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33"
" 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 "
"15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','t"
"exmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMME"
"NT: end icon text');\n"
Port {
PortNumber 1
Name "we"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "wr_ch"
Ports [1, 1]
Position [225, 96, 270, 114]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "2"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,20,356,423"
block_type "gatewayin"
block_version "9.1.01"
sg_icon_stat "45,18,1,1,white,yellow,0,bc55d28f,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33"
" 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 "
"15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 "
"]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ic"
"on text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','t"
"exmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMME"
"NT: end icon text');\n"
Port {
PortNumber 1
Name "wr_ch"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Line {
SrcBlock "freq_progam"
SrcPort 1
Points [10, 0]
DstBlock "wr_ch"
DstPort 1
}
Line {
SrcBlock "freq_progam"
SrcPort 2
DstBlock "wdata"
DstPort 1
}
Line {
SrcBlock "freq_progam"
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