gmsk_mod.mdl

This is GMS down upper converter and down converter in simulink. you may understand the structure in

	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
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	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
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	  ShowPortLabels	  "on"
	  SystemSampleTime	  "-1"
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	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
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	Block {
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	  RTWMemSecFuncInitTerm	  "Inherit from model"
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	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
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	  ShowPortLabels	  "on"
	  SystemSampleTime	  "-1"
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	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
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	Block {
	  BlockType		  Outport
	  Name			  "gmsk_data"
	  Position		  [555, 398, 585, 412]
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	Line {
	  SrcBlock		  "GMSK\nModulator\nBaseband"
	  SrcPort		  1
	  DstBlock		  "Complex to\nReal-Imag"
	  DstPort		  1
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	  SrcPort		  1
	  DstBlock		  "GMSK\nModulator\nBaseband"
	  DstPort		  1
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	Line {
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	  SrcPort		  1
	  DstBlock		  "Complex to\nReal-Imag1"
	  DstPort		  1
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	Line {
	  SrcBlock		  "Random Integer\nGenerator2"
	  SrcPort		  1
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	  DstPort		  1
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	  DstBlock		  "Complex to\nReal-Imag2"
	  DstPort		  1
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	Line {
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	  SrcBlock		  "Complex to\nReal-Imag5"
	  SrcPort		  2
	  Points		  [50, 0; 0, 30]
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	  SrcBlock		  "Complex to\nReal-Imag2"
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	  Points		  [50, 0; 0, 30]
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	Line {
	  SrcBlock		  "Complex to\nReal-Imag2"
	  SrcPort		  1
	  DstBlock		  "Mux2"
	  DstPort		  5
	}
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	  SrcBlock		  "Complex to\nReal-Imag5"
	  SrcPort		  1
	  DstBlock		  "Mux2"
	  DstPort		  11
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	  SrcBlock		  "Complex to\nReal-Imag4"
	  SrcPort		  1
	  DstBlock		  "Mux2"
	  DstPort		  9
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	  SrcBlock		  "Complex to\nReal-Imag1"
	  SrcPort		  2
	  Points		  [50, 0; 0, 30]
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	  DstPort		  4
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	Line {
	  SrcBlock		  "Complex to\nReal-Imag"
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	  Points		  [55, 0; 0, 30]
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	  DstPort		  2
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	Line {
	  SrcBlock		  "Complex to\nReal-Imag"
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	  DstPort		  1
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	  SrcPort		  1
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	  DstPort		  3
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	Line {
	  SrcBlock		  "GMSK\nModulator\nBaseband6"
	  SrcPort		  1
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	  DstPort		  1
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	Line {
	  SrcBlock		  "Complex to\nReal-Imag6"
	  SrcPort		  2
	  Points		  [45, 0; 0, 30]
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	  DstPort		  14
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	Line {
	  SrcBlock		  "Random Integer\nGenerator1"
	  SrcPort		  1
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	  DstPort		  1
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	Line {
	  SrcBlock		  "Complex to\nReal-Imag6"
	  SrcPort		  1
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	  DstPort		  13
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	Line {
	  SrcBlock		  "GMSK\nModulator\nBaseband7"
	  SrcPort		  1
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	  DstPort		  1
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	  SrcBlock		  "Complex to\nReal-Imag7"
	  SrcPort		  2
	  Points		  [50, 0; 0, 30]
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	  SrcBlock		  "Complex to\nReal-Imag7"
	  SrcPort		  1
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	  DstPort		  15
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	Line {
	  SrcBlock		  "Mux2"
	  SrcPort		  1
	  DstBlock		  "gmsk_data"
	  DstPort		  1
	}
      }
    }
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      BlockType		      Reference
      Name		      "Copyright"
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      SourceBlock	      "xbsCopyrightNotice_r4/Copyright"
      SourceType	      "Xilinx Copyright Notice Block"
      infoedit		      "
\nCopyright(C) 2008 by  Xilinx, Inc. All right"
"s reserved.<br>
\n<br>
\nThis file contains proprietary, confidential informa"
"tion of Xilinx, Inc., is distributed under license
\nfrom Xilinx, Inc., and m"
"ay be used, copied and/or disclosed only pursuant to the terms of a valid lic"
"ense
\nagreement with Xilinx, Inc. Xilinx hereby grants you a license to use "
"this file solely for design,
\nsimulation, implementation and creation of des"
"ign files limited to Xilinx devices or technologies. Use 
\nwith non-Xilinx d"
"evices or technologies is expressly prohibited and immediately terminates you"
"r license 
\nunless covered by a separate agreement.<br>
\n<br>
\nXilinx is p"
"roviding this design, code, or information \"as-is\" solely for use in develo"
"ping programs and 
\nsolutions for Xilinx devices, with no obligation on the "
"part of Xilinx to provide support. By providing
\nthis design, code, or infor"
"mation as one possible implementation of this feature, application or standar"
"d,
\nXilinx is making no representation that this implementation is free from"
" any claims of infringement. You
\nare responsible for obtaining any rights y"
"ou may require for your implementation. Xilinx expressly disclaims
\nany warr"
"anty whatsoever with respect to the adequacy of the implementation, including"
" but not limited to any
\nwarranties or representations that this implementat"
"ion is free from claims of infringement, implied warranties
\nof merchantabil"
"ity or fitness for a particular purpose.<br>
\n<br>
\nXilinx products are not"
" intended for use in life support appliances, devices, or systems. Use in suc"
"h 
\napplications is expressly prohibited.<br>
\n<br>
\nAny modifications tha"
"t are made to the Source Code are done at the user's sole risk and will be un"
"supported.<br>
\n<br>
\nThis copyright and support notice must be retained as"
" part of this text at all times. 
\n(c) Copyright 1995-2008 Xilinx, Inc. All "
"rights reserved.
\n      "
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	Block {
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    Block {
      BlockType		      ToWorkspace
      Name		      "To Workspace"
      Position		      [610, 115, 670, 145]
      VariableName	      "gmsk_data"
      MaxDataPoints	      "inf"
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      SaveFormat	      "Structure With Time"
    }
    Line {
      SrcBlock		      "8-channel GMSK modulator"
      SrcPort		      1
      DstBlock		      "Scale and Quantize"
      DstPort		      1
    }
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      SrcBlock		      "Scale and Quantize"
      SrcPort		      1
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    Annotation {
      Name		      "8-channel GMSK model for input vector capture"
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}