📄 mri.mdl
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NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "16385"
YMin "-65536"
YMax "65536"
DataFormat "Array"
LimitDataPoints off
}
Block {
BlockType Reference
Name "CIC_filter_1"
Ports [3, 3]
Position [330, 129, 425, 271]
SourceBlock "xbsIndex_r4/CIC Compiler 1.2 "
SourceType "Xilinx CIC Compiler 1.2 Block"
infoedit "Provides the ability to design and implemen"
"t Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices"
".<P><P>Hardware notes: Optional mapping to DSP48/E/A primitives."
filter_type "Decimation"
number_of_stages "4"
differential_delay "1"
number_of_channels "1"
input_data_width "17"
output_data_width "17"
sample_rate_changes "Fixed"
fixed_or_initial_rate "32"
minimum_rate "4"
maximum_rate "4"
ce off
sclr on
use_xtreme_dsp_slice off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
ip_name "CIC Compiler"
ip_version "1.2"
dsptool_ready "true"
structural_sim "false"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "cic_compiler_v1_2"
block_version "10.1.1"
sg_icon_stat "95,142,3,3,white,blue,0,a2809f18,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');"
"\ncolor('black');port_label('input',2,'nd');\ncolor('black');port_label('inpu"
"t',3,'sclr');\ncolor('black');port_label('output',1,'dout');\ncolor('black');"
"port_label('output',2,'rfd');\ncolor('black');port_label('output',3,'rdy');\n"
"fprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "CIC_filter_2"
Ports [3, 3]
Position [330, 299, 425, 441]
SourceBlock "xbsIndex_r4/CIC Compiler 1.2 "
SourceType "Xilinx CIC Compiler 1.2 Block"
infoedit "Provides the ability to design and implemen"
"t Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices"
".<P><P>Hardware notes: Optional mapping to DSP48/E/A primitives."
filter_type "Decimation"
number_of_stages "4"
differential_delay "1"
number_of_channels "1"
input_data_width "17"
output_data_width "17"
sample_rate_changes "Fixed"
fixed_or_initial_rate "32"
minimum_rate "4"
maximum_rate "4"
ce off
sclr on
use_xtreme_dsp_slice off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
ip_name "CIC Compiler"
ip_version "1.2"
dsptool_ready "true"
structural_sim "false"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "cic_compiler_v1_2"
block_version "10.1.1"
sg_icon_stat "95,142,3,3,white,blue,0,a2809f18,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');"
"\ncolor('black');port_label('input',2,'nd');\ncolor('black');port_label('inpu"
"t',3,'sclr');\ncolor('black');port_label('output',1,'dout');\ncolor('black');"
"port_label('output',2,'rfd');\ncolor('black');port_label('output',3,'rdy');\n"
"fprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Scope
Name "CIC_scope"
Ports [1]
Position [570, 175, 590, 195]
Floating off
Location [188, 365, 512, 604]
Open on
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
YMin "-65536"
YMax "65536"
DataFormat "Array"
LimitDataPoints off
}
Block {
BlockType Reference
Name "Constant"
Ports [0, 1]
Position [245, 187, 300, 213]
SourceBlock "xbsIndex_r4/Constant"
SourceType "Xilinx Constant Block Block"
arith_type "Boolean"
const "1"
n_bits "1"
bin_pt "0"
explicit_period off
period "1"
dsp48_infoedit "The use of this block for DSP48 instruction"
"s is deprecated. Please use the Opmode block."
equ "P=C"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "constant"
block_version "10.1.1"
sg_icon_stat "55,26,1,1,white,blue,0,06094819,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 2"
"7 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17"
" 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 2"
"6 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi"
"n icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMME"
"NT: end icon text');\n"
}
Block {
BlockType Reference
Name "Constant2"
Ports [0, 1]
Position [140, 472, 195, 498]
SourceBlock "xbsIndex_r4/Constant"
SourceType "Xilinx Constant Block Block"
arith_type "Boolean"
const "0"
n_bits "1"
bin_pt "0"
explicit_period on
period "1"
dsp48_infoedit "The use of this block for DSP48 instruction"
"s is deprecated. Please use the Opmode block."
equ "P=C"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "constant"
block_version "10.1.1"
sg_icon_stat "55,26,0,1,white,blue,0,72d575a1,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 2"
"7 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17"
" 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 2"
"6 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi"
"n icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMME"
"NT: end icon text');\n"
}
Block {
BlockType Reference
Name "DDS"
Ports [0, 1]
Position [120, 139, 215, 281]
SourceBlock "xbsIndex_r4/DDS Compiler 2.1 "
SourceType "Xilinx DDS Compiler 2.1 Block"
output_selection "Cosine"
negative_sine off
negative_cosine off
channels "1"
dds_clock_rate "170"
spurious_free_dynamic_range "96"
frequency_resolution "0.025"
rst off
en off
rfd off
rdy off
channel_pin off
explicit_period on
period "1"
phase_increment "Fixed"
output_frequency1 "66.9976806640625"
output_frequency2 "0"
output_frequency3 "0"
output_frequency4 "0"
output_frequency5 "0"
output_frequency6 "0"
output_frequency7 "0"
output_frequency8 "0"
output_frequency9 "0"
output_frequency10 "0"
output_frequency11 "0"
output_frequency12 "0"
output_frequency13 "0"
output_frequency14 "0"
output_frequency15 "0"
output_frequency16 "0"
phase_offset "None"
phase_offset_angles1 "0"
phase_offset_angles2 "0"
phase_offset_angles3 "0"
phase_offset_angles4 "0"
phase_offset_angles5 "0"
phase_offset_angles6 "0"
phase_offset_angles7 "0"
phase_offset_angles8 "0"
phase_offset_angles9 "0"
phase_offset_angles10 "0"
phase_offset_angles11 "0"
phase_offset_angles12 "0"
phase_offset_angles13 "0"
phase_offset_angles14 "0"
phase_offset_angles15 "0"
phase_offset_angles16 "0"
memory_type "Auto"
optimization_goal "Auto"
dsp48_use "Maximal"
noise_shaping "Auto"
latency_configuration "Auto"
latency "1"
accumulator_latency "One"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
por_mode "false"
ip_name "DDS Compiler"
ip_version "2.1"
dsptool_ready "true"
wrapper_available "true"
structural_sim "false"
clock_enable "true"
sclr_pin "false"
port_translation_map "{ 'ce' => 'en', 'sclr' => 'rst'}"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "dds_compiler_v2_1"
block_version "10.1.1"
sg_icon_stat "95,142,0,1,white,blue,0,d77b0339,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 95 95 0 ],[0 0 142 142 ],[0.77 0.82 0.91]);\npatch([22 6 28 6 22 4"
"7 54 61 88 67 47 32 54 32 47 67 88 61 54 47 22 ],[34 50 72 94 110 110 103 110"
" 110 89 109 94 72 50 35 55 34 34 41 34 34 ],[0.98 0.96 0.92]);\nplot([0 95 95"
" 0 0 ],[0 0 142 142 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf"
"('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cosin"
"e');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Delay_1"
Ports [2, 1]
Position [460, 157, 520, 213]
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, ea"
"ch link of which is an SRL16 followed by a flip-flop."
en on
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "delay"
block_version "10.1.1"
sg_icon_stat "60,56,2,1,white,blue,0,9c7d2b66,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 "
"34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 "
"49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56"
" 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be"
"gin icon text');\ncolor('black');port_label('input',2,'en');\ncolor('black');"
"disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Delay_2"
Ports [2, 1]
Position [460, 317, 520, 373]
SourceBlock "xbsIndex_r4/Delay"
SourceType "Xilinx Delay Block"
infoedit "Hardware notes: A delay line is a chain, ea"
"ch link of which is an SRL16 followed by a flip-flop."
en on
latency "1"
dbl_ovrd off
reg_retiming off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "delay"
block_version "10.1.1"
sg_icon_stat "60,56,2,1,white,blue,0,9c7d2b66,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 "
"34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 "
"49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56"
" 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be"
"gin icon text');\ncolor('black');port_label('input',2,'en');\ncolor('black');"
"disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "DownSample_1"
Ports [1, 1]
Position [550, 332, 610, 388]
SourceBlock "xbsIndex_r4/Down Sample"
SourceType "Xilinx Down Sampler Block"
infoedit "Hardware notes: Sample and Latency controls"
" determine the hardware implementation. The cost in hardware of different im"
"plementations varies considerably; press Help for details."
sample_ratio "16"
sample_phase "Last Value of Frame (most efficient)"
en off
latency "1"
dbl_ovrd off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "dsamp"
block_version "10.1.1"
sg_icon_stat "60,56,1,1,white,blue,0,4ce44f94,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 "
"34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 "
"49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56"
" 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be"
"gin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downar"
"row}16\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')"
";\n"
}
Block {
BlockType Reference
Name "DownSample_2"
Ports [1, 1]
Position [550, 417, 610, 473]
SourceBlock "xbsIndex_r4/Down Sample"
SourceType "Xilinx Down Sampler Block"
infoedit "Hardware notes: Sample and Latency controls"
" determine the hardware implementation. The cost in hardware of different im"
"plementations varies considerably; press Help for details."
sample_ratio "16"
sample_phase "Last Value of Frame (most efficient)"
en off
latency "1"
dbl_ovrd off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "dsamp"
block_version "10.1.1"
sg_icon_stat "60,56,1,1,white,blue,0,4ce44f94,right"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 "
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