readme.txt

cs8900A.rar是一个基于WinCE5.x下开发的芯片驱动程序。

       priority based on your platform.
       HookInterrupt(4, Ether_ISR);
   }

2) In OEMInterruptEnable/Disable/Done() functions in cfwp2.c, add
   {
    case SYSINTR_ETHER: /*It may not work for your processor.  Please find out the
     way to disable and enable the Ethernet interrupt. */
    _REGW (IPRC) = (_REGW(IPRC) & ETHERNET_IPRC_IRQ2_MASK)|ETHERNET_IPRC_IRQ2_INT;

    // for disable function it will be
    //_REGW (IPRC) = (_REGW(IPRC) & ETHERNET_IPRC_IRQ2_MASK);
    break;
   }

3) Create an ISR routine Ether_ISR in the "fwp2.src" file
   under .\Hal\Shx directory.

  .export _Ether_ISR
  LEAF_ENTRY _Ether_ISR
  mov.l #IPRC,R6 ; Interrupt priority register
  C (IPRC)
  mov.w @R6,R0
  mov.l #IPRC_IRQ2_MASK,R1 ;
  and R1,R0 ; Set IRQ2 to priority 0
  mov.w R0,@R6 ; Mask IRQ2
  ;
  mov.l #IRR0,R6 ; Interrupt request register 0
  (IRR0)
  mov.b @R6,R0
  mov #(~IRR0_IRQ2R & 0xFF),R0 ; Clear IRQ2 interrupt flag
  and R1,R0 ;
  mov.b R0,@R6 ;
  rts
  mov #SYSINTR_ETHER, r0

4) Put "SYSINTR_ETHER" in both "OALintr.h" and "OALintr.inc" files.

  SYSINTR_ETHER: SYSINTR_FIRMWARE+10
  SYSINTR_ETHER: .equ SYSINTR_FIRMWARE+10

  They are the interrupt IDs used by the CE kernel. SYSINTR_ETHER is independent from 
  the interrupt line connection between Processor and MAC.

5) If you can not use SYSINTR_ETHER = SYSINTR_FIRMWARE+10, and would like to define
   your own value, make sure your define isn't conflict with other interrupts.

   Assume the followings are the new defines:
    
   SYSINTR_ETHER: SYSINTR_FIRMWARE+??
   SYSINTR_ETHER: .equ SYSINTR_FIRMWARE+??

   In CrystalInitialize() in CS8900A.c, change one line from:

   #if ( defined(ARM_PROCESSOR) || defined(SHx_PROCESSOR))
	  /* Since SYSINTR_ETHER = SYSINTR_FIRMWARE+10 defined in OALint.h, 
	     pChip->Config.IntLine must be 10 here for CE kernel to map CS8900 ISR
	     to SYSINTR_ETHER. */
      pChip->Config.IntLine = 10; //Change this line only.
 
   to:

    pChip->Config.IntLine = ?? ; //SYSINTR_ETHER - SYSINTR_FIRMWARE
 


=================================================================================
===============         Required Modifications for ARM           ================
=================================================================================

The CS8900A WinCE driver supports only the IO mode. The ARM's address lines should be 
connected to CS8900A in a special way to enable IO mode on CS8900A.  Thus, the ARM's
address lines become  CS8900A's IO port lines. 

First, ARM_PROCESSOR must be defined in the sources file:
CDEFINES=$(CDEFINES) -DNDIS_MINIPORT_DRIVER  -DARM_PROCESSOR 

Second, change the values of CS8900_INTERRUPT_REQUEST_PIN_NUM and 
CS8900_IOPORT_MEM_ADDR in cshrd.h. 

The CS8900A has four interrupt request output pins that can be connected directly 
to Processor. Only one interrupt output pin is connected to ARM.
CS8900_INTERRUPT_PIN_NUM defines which interrupt pin is used.
 0:  INTRQ0
 1:  INTRQ1
 2:  INTRQ2
 3:  INTRQ3
#define CS8900_INTERRUPT_REQUEST_PIN_NUM     0 /* or other number: 0-3 */

For ARM and Strong ARM, CS8900_IOPORT_MEM_ADDR is the un-buffered & un-cashed 
virtual address(range 0xA0000000-0xBFFFFFFF). Its buffered & cashed virtual address 
(ragne 0x80000000-0x9FFFFFFF) should be defined in OEMAddressTable.

#define CS8900_IOPORT_MEM_ADDR     0x????????L


Third, an IRQ line must be assigned to the CS8900A Ethernet controller.
You may need to modify WinCE's kernel to hook up the Ethernet Interrupt to the
ARM processor. Please read WinCE's on-line help first to get some ISR ideas.  
you need to modify WinCE's kernel to hook up the Ethernet Interrupt to the
ARM processor.  

The following instructions will give you ideas how to modify the 
WinCE kernel.

****** Note: Must Read!!!!!!!!!!! ******** 
The following description is based on CE 3.x.  So, it just give
you the ideas but not the exact way for CE 4.x or CE 5.x.
 
1) In OEMInterruptEnable/Disable/Done() functions in 
   platform\YourPlatform\kernel\HAL\cfwsarm.c (or other files), modify the code to enable and
   disable the Ethernet interrupt according to your target board:

   {
    case SYSINTR_ETHER: /*It may not work for your processor.  Please find out the
     way to disable and enable the Ethernet interrupt. */
     _REGW(IPRC) = (_REGW(IPRC) & ETHERNET_IPRC_IRQ2_MASK)|ETHERNET_IPRC_IRQ2_INT;

     // for disable function it will be
     //_REGW (IPRC) = (_REGW(IPRC) & ETHERNET_IPRC_IRQ2_MASK);
     break;
    }


2) Put "SYSINTR_ETHER" in both "OALintr.h" and "OALintr.inc" files.

   SYSINTR_ETHER: SYSINTR_FIRMWARE+10
   SYSINTR_ETHER: .equ SYSINTR_FIRMWARE+10

   They are the interrupt IDs used by the CE kernel. SYSINTR_ETHER is independent from 
   the interrupt line connection between Processor and MAC.


3) If you can not use SYSINTR_ETHER = SYSINTR_FIRMWARE+10, and would like to define
   your own value, make sure your define isn't conflict with other interrupts.

   Assume the followings are the new defines:
    
   SYSINTR_ETHER: SYSINTR_FIRMWARE+??
   SYSINTR_ETHER: .equ SYSINTR_FIRMWARE+??

   In CrystalInitialize() in CS8900A.c, change one line from:

   #if ( defined(ARM_PROCESSOR) || defined(SHx_PROCESSOR))
	  /* Since SYSINTR_ETHER = SYSINTR_FIRMWARE+10 defined in OALint.h, 
	     pChip->Config.IntLine must be 10 here for CE kernel to map CS8900 ISR
	     to SYSINTR_ETHER. */
      pChip->Config.IntLine = 10; //Change this line only.
 
   to:

    pChip->Config.IntLine = ?? ; //SYSINTR_ETHER - SYSINTR_FIRMWARE
 
 
4) If your ARM type is SA1110, ARM920, or ARM720, look at INT1110.c, INT920.c, or INT720O.c
   in the .\HAL\ARM directory respectively. Modify the following code segment in 
   EMInterruptHandler() so  ArmInterruptHandler() can be correctly called when Interrupts
   are coming.
     
  The following code is extracted from SA1110.c. It needs modifications to
  correctly read and write interrupt registers
		  .
	  } else if(my_sa1100_intreg & GPIO_1) {
      	//Clear the GPIO interrupt
		sa1100_gpio->gedr = GPIO_1;
	    
        //
        // For SA1100, we allow the system tick only to interrupt any of the 
        // Odo FPGA interrupt handlers. This is to show the use of nested 
        // interrupts on ARM.
        //
        dwSavedICMR = sa1100_int_ctlr->icmr;
		sa1100_int_ctlr->icmr = OS_TIMER0;
        INTERRUPTS_ON();
        
        // Call common FPGA interrupt handler code with TIMER interrupt enabled.
	    dwRet = ArmInterruptHandler();
        
        INTERRUPTS_OFF();
		sa1100_int_ctlr->icmr = dwSavedICMR;
        
	    return dwRet;
    }


5) Modify the code segment in ArmInterruptHandler() in the .\HAL\ARM\ARMint.c:

    else if ( (my_odo_isr_reg & odo_etherIntr) != 0 )
    {
        // mask the debug Ethernet interrupt
        odo_cpu->odo_cpuMr &= ~odo_etherIntr;
        GOTO_EXIT(SYSINTR_ETHER);
    }
 
    so it can properly determine if there is an Ethernet Interrupt. If yes, then 
	clear the Ethernet Interrupt mask or do nothing depending on your target board.
	GOTO_EXIT(SYSINTR_ETHER) must be called if there is an Ethernet Interrupt.


6) Since WinCE's ISR can process only one Interrupt at a time, 
   modify the code segment in ArmInterruptHandler() in the .\HAL\ARM\ARMint.c:

EXIT: 
    //
    // Since all of the FPGA interrupts are multiplexed on one signal to the CPU
    // we need to be careful when multiple interrupts are pending. We have
    // cleared the interrupt at the CPU early on. If there's another interrupt
    // that needs processing, we need to force a new interrupt. We do this by
    // clearing the cpuMr register and reinstating it.
    //
    wMrTemp = odo_cpu->odo_cpuMr;
    odo_cpu->odo_cpuMr = 0x0000;
    odo_cpu->odo_cpuMr = wMrTemp;
    return (iRet);

    according to your target board so the pending interrupts can be processed 
	next time.