📄 stm32.cfg
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# script for stm32if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME stm32}if { [info exists ENDIAN] } { set _ENDIAN $ENDIAN } else { set _ENDIAN little}# jtag speedjtag_khz 500jtag_nsrst_delay 100jtag_ntrst_delay 100#use combined on interfaces or targets that can't set TRST/SRST separatelyreset_config trst_and_srst#jtag scan chainif { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID} else { # See STM Document RM0008 # Section 26.6.3 set _CPUTAPID 0x3ba00477}jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPIDif { [info exists BSTAPID ] } { set _BSTAPID $BSTAPID} else { # See STM Document RM0008 # Section 26.6.2 # Medium Density RevA set _BSTAPID 0x06410041 # Rev B and Rev Z set _BSTAPID 0x16410041 # High Density Devices, Rev A set _BSTAPID 0x06414041} jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPIDset _TARGETNAME [format "%s.cpu" $_CHIPNAME]target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0flash bank stm32x 0 0 0 0 0# For more information about the configuration files, take a look at:# openocd.texi
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