📄 pentium.txt
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LGDT mem48 lgdt descriptor 6
LIDT mem48 lidt descriptor 6
LLDT reg16 lldt ax 9
LLDT mem16 lldt selector 9
LMSW reg16 lmsw ax 8
LMSW mem16 lmsw machine 8
LOCK lock 1
LODS [segreg:]src lods es:source 2
LODSB [[segreg:]src] lodsb 2
LODSW [[segreg:]src] lodsw 2
LODSD [[segreg:]src] lodsd 2
LOOP label loop wend 5, 6
LOOPE label loope again 7, 8
LOOPZ label loopz again 7, 8
LOOPNE label loopne for_next 7, 8
LOOPNZ label loopnz for_next 7, 8
LSL reg,reg lsl ax,bx 8
LSL reg,mem lsl cx,seg_lim 8
LTR reg16 ltr ax 10
LTR mem16 ltr task 10
MOV reg,reg mov bp,sp 1
MOV mem,reg mov array[di],bx 1
MOV reg,mem mov bx,pointer 1
MOV mem,immed mov [bx],15 1
MOV reg,immed mov cx,256 1
MOV mem,accum mov total,ax 1
MOV accum,mem mov al,string 1
MOV segreg,reg16 mov ds,ax 2, 3
MOV segreg,mem16 mov es,psp 2, 3
MOV reg16,segreg mov ax,ds 1
MOV mem16,segreg mov stack_save,ss 1
MOV reg32,controlreg mov eax,cr0 22
mov eax,cr2 12
mov eax,cr3 21, 46
mov eax,cr4 14
MOV controlreg,reg32 mov cr0,eax 4
MOV reg32,debugreg mov edx,dr0 DR0-DR3,DR6,DR7=11;
DR4,DR5=12
MOV debugreg,reg32 mov dr0,ecx DR0-DR3,DR6,DR7=11;
DR4,DR5=12
MOVS [ES:]dest,
[segreg:]src movs dest,es:source 4
MOVSB [[ES:]dest,
[segreg:]src] movsb 4
MOVSW [[ES:]dest,
[segreg:]src] movsw 4
MOVSD [[ES:]dest,
[segreg:]src] movsd 4
MOVSX reg,reg movsx bx,al 3
MOVSX reg,mem movsx eax,bsign 3
MOVZX reg,reg movzx bx,al 3
MOVZX reg,mem movzx eax,bunsign 3
MUL reg mul bx 8,16-bit=11;
MUL mem mul WORD PTR [bx] 32-bit=10
NEG reg neg ax 1
NEG mem neg balance 3
NOP nop 1
NOT reg not ax 1
NOT mem not masker 3
OR reg,reg or ax,dx 1
OR mem,reg or bits,dx 3
OR reg,mem or dx,color[di] 2
OR reg,immed or dx,110110b 1
OR mem,immed or flag_rec,8 3
OR accum,immed or ax,40h 1
OUT immed8,accum out 60h,al 12, pm=9,26, VM=24
OUT DX,accum out dx,ax 12, pm=9,25 VM=24
OUTS DX,[segreg:]src outs dx,buffer 13, pm=10,27, VM=24
OUTSB [DX,[segreg:]src] outsb 13, pm=10,27, VM=24
OUTSW [DX,[segreg:]src] outsw 13, pm=10,27, VM=24
OUTSD [DX,[segreg:]src] outsd 13, pm=10,27, VM=24
POP reg pop cx 1
POP mem pop param 3
POP segreg pop es 3
POPA popa 5
POPAD popad 5
POPF popf 6, pm=4
POPFD popfd 6, pm=4
PUSH reg push dx 1
PUSH mem push [di] 2
PUSH segreg push es 1
PUSH immed push 15000 1
PUSHA pusha 5
PUSHAD pushad 5
PUSHF pushf 4, pm=3
PUSHFD pushfd 4, pm=3
RCL reg,1 rcl dx,1 1
RCL mem,1 rcl WORD PTR [si],1 3
RCL reg,CL rcl dx,cl 7-24
RCL mem,CL rcl masker,cl 9-26
RCL reg,immed8 rcl bx,5 8-25
RCL mem,immed8 rcl WORD PTR [bp+8],3 10-27
RCR reg,1 rcr bl,1 1
RCR mem,1 rcr WORD PTR m32[0],1 3
RCR reg,CL rcr bl,cl 7-24
RCR mem,CL rcl WORD PTR [bx=di],cl 9-26
RCR reg,immed8 rcr si,9 8-25
RCR mem,immed8 rcr masker,3 10-27
ROL reg,1 rol ax,1 1
ROL mem,1 rol bits,1 3
ROL reg,CL rol ax,cl 4
ROL mem,CL rol color,cl 4
ROL reg,immed8 rol ax,13 1
ROL mem,immed8 rol BYTE PTR [bx],10 3
ROR reg,1 ror ax,1 1
ROR mem,1 ror WORD PTR [bx],1 3
ROR reg,CL ror dx,cl 4
ROR mem,CL ror color,cl 4
ROR reg,immed8 ror bl,3 1
ROR mem,immed8 ror bits,6 3
RDMSR rdmsr 20-24
REP INS dest,DX rep ins dest,dx 11+3n, pm=(8,25)+3n*
REP MOVS dest,src rep movs dest,source 6, 13n
REP OUTS DX,src rep outs dx,source 13+4n, pm=(10,27)+4n*
REP LODS dest rep lods dest 7, 7+3n
REP STOS dest rep stos dest 6, 9+3n
(*First protected mode timing: CPL < or = IOPL. Second timing: CPL > IOPL.)
REPE CMPS src,dest repe cmps src,dest 7, 9+4n
REPE SCAS dest repe scas dest 7, 9+4n
REPNE CMPS src,dest repne cmps src,dest 7, 8+4n
REPNE SCAS dest repne scas dest 7, 9+4n
RETN retn 2
RETN immed16 retn 8 3
RETF retf 4, 23
RETF immed16 retf 32 4, 23
RSM rsm 83
SAHF sahf 2
SAL reg,1 sal bx,1 1
SAL mem,1 sal WORD PTR m32[0],1 3
SAL reg,CL sal ah,cl 4
SAL mem,CL sal BYTE PTR [di],cl 4
SAL reg,immed sal cx,6 1
SAL mem,immed sal array[bx+di],14 3
SAR reg,1 sar di,1 1
SAR mem,1 sar count,1 3
SAR reg,CL sar bx,cl 4
SAR mem,CL sar sign,cl 4
SAR reg,immed sar bx,5 1
SAR mem,immed sar sign_count,3 3
SHL reg,1 shl si,1 1
SHL mem,1 shl index,1 3
SHL reg,CL shl di,cl 4
SHL mem,CL shl index,cl 4
SHL reg,immed shl di,2 1
SHL mem,immed shl unsign,4 3
SHR reg,1 shr dh,1 1
SHR mem,1 shr unsign[di],1 3
SHR reg,CL shr dx,cl 4
SHR mem,CL shr WORD PTR m32[2],cl 4
SHR reg,immed shr bx,8 1
SHR mem,immed shr mem16,11 3
SBB accum,immed sbb ax,320 1
SBB reg,immed sbb dx,45 1
SBB mem,immed sbb WORD PTR m32[2],40 3
SBB reg,reg sbb dx,cx 1
SBB mem,reg sbb WORD PTR m32[2],dx 3
SBB reg,mem sbb dx,WORD PTR m32[2] 2
SCAS [ES]dest scas es:destin 4
SCASB scasb 4
SCASW scasw 4
SCASD scasd 4
SETcondition reg8 setc dh 1
SETcondition mem8 setle flag 2
SGDT mem48 sgdt descriptor 4
SIDT mem48 sidt descriptor 4
SHLD reg16,reg16,immed8 shld ax,dx,10 4
SHLD reg32,reg32,immed8
SHLD mem16,reg16,immed8 shld bits,cx,5 4
SHLD mem32,reg32,immed8
SHLD reg16,reg16,CL shld ax,dx,cl 4
SHLD reg32,reg32,CL
SHLD mem16,reg16,CL shld masker,ax,cl 5
SHLD mem32,reg32,CL
SHRD reg16,reg16,immed8 shrd cx,si,3 4
SHRD reg32,reg32,immed8
SHRD mem16,reg16,immed8 shrd [di],dx,5 4
SHRD mem32,reg32,immed8
SHRD reg16,reg16,CL shrd ax,dx,cl 4
SHRD reg32,reg32,CL
SHRD mem16,reg16,CL shrd [bx],ax,cl 5
SHRD mem32,reg32,CL
SLDT reg16 sldt ax 2
SLDT mem16 sldt selector 2
SMSW reg16 smsw ax 4
SMSW mem16 smsw machine 4
STC stc 2
STD std 2
STI sti 7
STOS [ES:]dest stor es:dstring 3
STOSB [[ES:]dest] stosb 3
STOSW [[ES:]dest] stosw 3
STOSD [[ES:]dest] stosd 3
STR reg16 str cx 2
STR mem16 str taskreg 2
SUB reg,reg sub ax,bx 1
SUB mem,reg sub array[di],bi 3
SUB reg,mem sub al,[bx] 2
SUB reg,immed sub bl,7 1
SUB mem,immed sub total,4000 3
SUB accum,immed sub ax,32000 1
TEST reg,reg test dx,bx 1
TEST mem,reg test flags,dx 2
TEST reg,immed test cx,30h 1
TEST mem,immed test masker,1 2
TEST accum,immed test ax,90h 1
VERR reg16 verr ax 7
VERR mem16 verr selector 7
VERW reg16 verw cx 7
VERW mem16 verw selector 7
WAIT wait 1
WBINVD wbinvd 2000+
WRMSR wrmsr 30-45
XADD reg,reg xadd dl,al 3
XADD mem,reg xadd string,bl 4
XCHG reg,reg xchg cx,dx 3
XCHG reg,mem xchg bx,pointer 3
XCHG mem,reg xchg [bx],ax 3
XCHG accum,reg xchg ax,cx 2
XCHG reg,accum xchg cx,ax 2
XLAT [[segreg:]mem] xlat 4
XLATB [[segreg:]mem] xlatb es:table 4
XOR reg,reg xor cx,bx 1
XOR reg,mem xor cx,flags 2
XOR mem,reg xor [bp+10],cx 3
XOR reg,immed xor bl,1 1
XOR mem,immed xor switches[bx],101b 3
XOR accum,immed xor ax,01010101b 1
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