📄 pentium.txt
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Notes on Intel(R) Pentium(TM) Processor
(c) Copyright Microsoft Corp. 1993
This file contains the following information:
- Implementation of the .586 and .586P directives
- New instructions for the Intel(R) Pentium(TM) processor
- Pentium clock cycles for all instructions
=============================================================================
.586 and .586P Directives
-------------------------
The .586 directive enables assembly of non-privileged instructions
available for the Pentium processor. The .586P directive enables
privileged instructions in addition to the non-privileged instructions
for the Pentium.
The following example demonstrates implementation of the .586 directive.
.model small, C
.586
.data
; .586 gives 110100111111y = 0D3Fh
; .586p gives 110110111111y = 0DBFh
var1 dw @cpu
IF @Cpu AND 0100000y
%echo Pentium instructions enabled.
ELSE
%echo Pentium instructions Not enabled.
ENDIF
end
=============================================================================
New Pentium Instructions
------------------------
The new Pentium instructions are extensions to the Intel486 instruction
set; for information on instructions for the 8086, 8088, 80286, 80386,
and 80486 processors, see Chapter 4, "Processor," in the Microsoft MASM
Reference. For additional information on the new Pentium instructions,
refer to you Intel documentation.
CMPXCHG8B Compare and Exchange 8 Bytes
Compares the 64-bit value in EDX:EAX with a 64-bit value in memory. If
they are equal, the 64-bit value in memory is replaced by the value in
ECX:EBX. Otherwise, the value in memory is loaded into EDX:EAX.
Flags: The ZF flag is set if the destination operand and EDX:EAX are
equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are
unaffected.
Encoding: 00001111 11000111 mod 001 r/m
Syntax Example Clock Cycles
------ ------- -----------
CMPXCHG8B mem64 cmpxchg8b [bx] 10
-----------------------------------------------------------------------------
CPUID CPU Identification
Syntax: CPUID
Provides information to the software about the model of microprocessor
on which it is executing. An input value loaded into the EAX register
for this instruction indicates what information should be returned by
the CPUID instruction.
Following execution of the CPUID instruction with zero in EAX, the EAX
register contains the highest input value understood by the CPUID
instruction. For the Pentium, the value in EAX will be 1. Also included
in this output is a vendor identification string contained in EBX, EDX,
and ECX. EBX contains the first four characters, EDX the next four, and
ECX the last four. For Intel processors, the vendor identification string
is "GenuineIntel".
Following execution of the CPUID instruction with input value 1 in EAX,
EAX[3:0] contains the stepping ID of the microprocessor, EAX[7:4]
contains the model (the first model will be indicated by 0001B) and
EAX[11:8] contains the family (5 for the Pentium). EAX[31:12], EBX, and
ECX are reserved. The Pentium processor sets the feature register, EDX,
to 1BFH, indicating which features the Pentium supports. A feature flag
set to 1 indicates that the corresponding feature is supported.
Flags: No flags affected.
Encoding: 00001111 10100010
Syntax Example Clock Cycles
------ ------- -----------
CPUID cpuid 14
-----------------------------------------------------------------------------
MOV Move to/from Control Registers
Store or load the Control Registers (CR0, CR2, CR3, CR4) to or from a
general purpose register.
Flags: The OF, SF, ZF, AF, PF, and CF flags are undefined.
Encoding: 00001111 00100010 11 eee reg (Move to Control Register)
Syntax Example Clock Cycles
------ ------- -----------
MOV reg32,controlreg mov cr0,eax 22
mov cr2,eax 12
mov cr3,eax 21,46
mov cr4,eax 14
Encoding: 00001111 00100000 11 eee reg (Move from Control Register)
Syntax Example Clock Cycles
------ ------- -----------
MOV controlreg,reg32 mov eax,cr0 4
-----------------------------------------------------------------------------
RDMSR Read from Model-Specific Register
The value in ECX specifies one of the 64-bit Model-Specific Registers of
the Pentium processor. The content of that Model-Specific Register is
copied into EDX:EAX. EDX is loaded with the high-order 32 bits, and EAX
is loaded with the low-order 32 bits.
Flags: No flags affected.
Encoding: 00001111 00110010
Syntax Example Clock Cycles
------ ------- -----------
RDMSR rdmsr 20-24
-----------------------------------------------------------------------------
RDTSC Read from Time Stamp Counter
Copies the contents of the Time Stamp Counter (TSC) into EDX EAX. (The
Pentium maintains a 64-bit Time Stamp Counter (TSC) that is incremented
every clock cycle.) When the Current Privilege Level is 0, the state of
the TSD bit in CR4 does not affect the operation of this instruction.
When the CPL is equal to 1, 2, or 3, the TSC may be read only if the TSD
bit in CR4 is 0. Only a supervisor level program may modify the value of
the TSC.
Flags: No flags affected.
Encoding: 00001111 00110001
Syntax Example Clock Cycles
------ ------- -----------
RDTSC rdtsc 6, 11
-----------------------------------------------------------------------------
RSM Resume from System Management Mode
The processor state is restored from the dump created upon entrance to
System Management Mode. However, the contents of the model-specific
registers are not affected. The processor leaves SMM and returns control
to the interrupted application or operating system. If the processor
detects any invalid state information, it enters the shutdown state.
Flags: All flags are affected.
Encoding: 00001111 10101010
Syntax Example Clock Cycles
------ ------- -----------
RSM rsm 83
-----------------------------------------------------------------------------
WRMSR Write to Model-Specific Register
The value in ECX specifies one of the 64-bit Model-Specific Registers of
the Pentium processor. The content of EDX:EAX is copied to that Model-
Specific Register. The high-order 32 bits are copied from EDX, and the
low-order 32 bits are copied from EAX.
Flags: No flags affected.
Encoding: 00001111 00110000
Syntax Example Clock Cycles
------ ------- -----------
WRMSR wrmsr 30-45
=============================================================================
Pentium Clock Cycles
--------------------
The following table contains clock cycles information for all Intel
Pentium processor instructions. For more detailed information on clock
cycles for these instructions, see your Intel documentation. For more
general information on these instructions, see Chapter 4, "Processor,"
and Chapter 5, "Coprocessor," in the Microsoft MASM Reference.
Instruction Syntax Example Clock Cycles
------------------ ------- ------------
AAA aaa 3
AAD aad 10
AAM aam 18
AAS aas 3
ADC reg,reg adc dx,cx 1
ADC mem,reg adc WORD PTR m16[2],dx 3
ADC reg,mem adc dx,DWORD PTR m32[2] 2
ADD reg,reg add ax,bx 1
ADD mem,reg add total, cx 3
ADD reg,mem add cx,incr 2
ADD reg,immed add bx,6 1
ADD mem,immed add pointers[bx][si],6 3
ADD accum,immed add ax,10 1
AND reg,reg and dx,bx 1
AND mem,reg and bitmask,bx 3
AND reg,mem and bx,masker 2
AND reg,immed and dx,0F7h 1
AND mem,immed and masker,100lb 3
AND accum,immed and ax,0B6h 1
ARPL reg,reg arpl ax,cx pm=7
ARPL mem,reg arpl selector,dx pm=7
BOUND reg16,mem32 bound di,base-4 8 (within bounds);
int+32 (out of bounds)
BOUND reg32,mem64 bound di,base-4 8 (within bounds);
int+32 (out of bounds)
BSF reg16,reg16 bsf cx,bx 6-34
BSF reg32,reg32 bsf cx,bx 6-42
BSF reg16,mem16 bsf ecx,bitmask 6-35
BSF reg32,mem32 bsf ecx,bitmask 6-43
BSR reg16,reg16 bsr cx,dx 7-39
BSR reg32,reg32 bsr cx,dx 7-71
BSR reg16,mem16 bsr eax,bitmask 7-40
BSR reg32,mem32 bsr eax,bitmask 7-72
BSWAP reg32 bswap ebx 1
BT reg16,immed8* bt ax,4 4
BT mem16,immed8* bt [bx],4 4
BT reg16,reg16* bt ax,bx 4
BT mem16,reg16* bt [bx],dx 9
* Operands can also be 32 bits
BTC reg16,immed8* btc edi,4 7
BTC mem16,immed8* btc color[di],4 8
BTC reg16,reg16* btc eax,ebx 7
BTC mem16,reg16* btc [bp+8],si 13
* Operands can also be 32 bits
BTR reg16,immed8* btr bx,17 7
BTR mem16,immed8* btr [bx],27 8
BTR reg16,reg16* btr cx,di 7
BTR mem16,reg16* btr rotate,cx 13
* Operands can also be 32 bits
BTS reg16,immed8* bts ax,4 7
BTS mem16,immed8* bts maskit,4 8
BTS reg16,reg16* bts bx,ax 7
BTS mem16,reg16* bts flags[bx],cx 13
* Operands can also be 32 bits
CALL label call upcase 1
call distant 4
CALL reg call ax 2
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