oren_mtd.h

M-System DOC(Disk on a Chip) Flash芯片映像读写工具, 可以进行二片Flash芯片的内容互相拷贝, 提高烧录程序的效率.

/*******************************     FOUNDRY_TEST_REG      ************************/
#define OREN_SOFT_RESET                  0x80
#define OREN_ICMU_CLOCK_ON_IRQ_PIN       0x08   /* When set ICMU will be output on external pin */ 
#define OREN_BDETECT_TEST_MODE           0x04   /* In this mode the boot detector will be incremented by 11H instead of 01H */
#define OREN_DOWNLOAD_TEST_MODE          0x02   /* Download test mode - data is downloaded from D[7:0] instead of the flash */
#define OREN_FLASH_TEST_MODE             0x01   /* When set provides all the pin signals on the I/O pins */

/******************************* HW_PROTECTION_CONTROL_REG *************************/
#define OREN_PROTECTION_DNLD_ENABLED     0x01
#define OREN_FLASH_EMPTY                 0x02
#define OREN_NO_OF_FLASH_RD_SEQ_BITS     0x0C
#define OREN_FOUNDRY_KEY_ENABLE          0x80  

/*******************************    OUTPUT_CONTROL_REG     **************************/
#define OREN_ASSERT_BUSY_DURING_DNLD     0x01
#define OREN_DISABLE_PULL_UP_BITS        0x06
#define OREN_RAM_ADDRESS_LE              0x08 
#define OREN_SOFTWRAE_LOCK_ENABLED       0x10 

/*******************************     ICMU_CONTROL_REG      *************************/
#define OREN_EXTERNAL_CLOCK_ENABLE       0x01   /* Disable the ICMU operation and move to external clock operation */
#define OREN_CLOCK_AVAILABLE             0x02   /* Clock available for the DOC Asic */
#define OREN_CORRECTION_FACTOR_WRITE_EN  0x04
 
/*******************************     CLOCK_COUNTER_REG     *************************/
#define OREN_CLOCK_COUNTER_RESET         0x8000 /* The counter starts to count from zero */
#define OREN_CLOCK_COUNTER_STOP          0x4000 /* The counter is stopped until CLOCK_COUNTER_RESET is set */  
#define OREN_CLOCK_COUNTER_BITS          0x3FFF   
 
/*******************************    LPC_CONFIGURATION_REG  *************************/
#define OREN_LPC_IO_WINDOW               0x8000 /* Refer to bit in the high byte */
#define OREN_LPC_PROGRAMMABLE_DECODE_EN  0x4000   
#define OREN_LPC_STRAPPING_DECODE_EN     0x2000 
#define OREN_LPC_PROGRAMMABLE_ADDR_BITS  0x1FFF

/*******************************      LPC_IO_INDEX_REG     **************************/ 
#define OREN_LPC_IO_INDEX_REG_BITS       0x3F

/*******************************        LPC_DMA_REG        **************************/ 
#define OREN_DMA_CHANNEL_BITS            0x07   /* The DOC will request to DMA in this Channel */
#define OREN_DMA_INITIATE_DMA_REQUEST    0x08
#define OREN_DMA_LDRQ_SIGNAL_EN          0x10
#define OREN_DMA_CYCLE_SIZE_BITS         0x60

/*******************************      LPC_INTERRUPT_REG    **************************/
#define OREN_LPC_INT_NUMBER_BITS         0x1F   /* Interrupt will be requested by DOC on SERIRQ */
#define OREN_LPC_EDGE_INT                0x20
#define OREN_LPC_ENABLE_DMA_INT          0x40
#define OREN_LPC_DMA_INT_PENDING         0x80

/*******************************     FLASH_CONTROL_REG     **************************/
#define OREN_FSE_SIGNAL_ACTIVE           0x40   /* Controls the assertion of the FSE# bit */
#define OREN_FWP_SIGNAL_ACTIVE           0x20   /* After protocol violation detected we must clear this bit */
#define OREN_FCE_SIGNAL_ACTIVE           0x10   /* Controls the assertion of the CE# to the BANK defined by the BANK bits */ 
#define OREN_BANK_BITS                   0x0c   /* Control with which bank we are working */
#define OREN_BANK_BITS_SHIFT             0x2    /* Shift of the bank bits in the register */
#define OREN_HIGH_BYTE_LANE              0x02   /* When FLASH_ACCESS is 16 bit and SYSTEM_INTERLEAVE is 1 -> controls to which lane we would write to */
#define OREN_ACTUAL_INTERLEAVE           0x01   /* 1 - Access to the flash is Performed in 8 bits , 1- Access is Performed in 16 bits (or to two 8 bits devices */

/*******************************    FLASH_STATUS_REG        *************************/
#define OREN_FLASH_READY                 0x01   /* FLASH READY/BUSY# output signal */
#define OREN_DATA_FIFO_FULL              0x02   /* Data FIFO is full  */  
#define OREN_DATA_FIFO_EMPTY             0x04   /* Data FIFO is empty */  
#define OREN_DATA_FIFO_FLOW              0x08   /* Data O.F/U.F detected & will be cleared after the current access is finished  */  
#define OREN_SEQUENCE_ERROR_DETECTED     0x10   /* Sequence Error detected & will be cleared only by FLASH reset command */
#define OREN_PROTECTION_ERROR_DETECTED   0x20   /* Protection Error & will be cleared after FLASH reset command */
#define OREN_SYSTEM_INTERLEAVE_2         0x40   /* Reflection of system interleave */
#define OREN_SINGLE_16BIT_FLASH_CONNECT  0x80   /* Indicates that a 16 bit single flash is connected to the DOC */

/*******************************  FLASH_ACCESS_CONFIG_REG    ************************/
#define OREN_FRE_FWE_ACCESS_CYCLES_BITS  0x07   /* Duration of the FRE/FWE access cycle (access duration = FRE_FWE_ACCESS_CYCLES_BITS + 1) */
#define OREN_RISE_EDGE_DELAY_EN          0x08   /* Enable of delay of rising edge of half a clock */        

/*******************************      ECC_CONTROL_REG_0      ************************/
#define OREN_DATA_COUNTER_BITS           0x07FF    
#define OREN_BCH_EN                      0x0800     
#define OREN_HAMMING_EN                  0x1000
#define OREN_ECC_IN_SW                   0x2000  
#define OREN_AUTO_ECC_READ_WRITE_EN      0x4000     
#define OREN_FLASH_READ_MODE             0x8000 /* Host is doing a read operation */

/*******************************      ECC_CONTROL_REG_1      ************************/
#define OREN_HM_DATA_NUM_BITS            0x0F
#define OREN_ECC_BUSY                    0x10
#define OREN_PAGE_READ_IS_USED           0x20
#define OREN_IGNORE_DATA                 0x40
#define OREN_BCH_SYNDROM_ERROR           0x80                 

/*******************************    PROTECTION_STATUS_REG    *************************/
#define OREN_FOUNDRY_OTP_LOCKED          0x01
#define OREN_CUSTOMER_OTP_LOCKED         0x02
#define OREN_PROTECTION_ERROR            0x08
#define OREN_LOCK_INPUT_ASSERTED         0x10
#define OREN_PROTECTION_ENABLED          0x20
#define OREN_FOUNDRY_OTP_REVISION_BITS   0xC0

/*******************************         DPS0_STATUS_REG     *************************/
#define OREN_MTD_READ_PROTECTED          0x01 
#define OREN_MTD_WRITE_PROTECTED         0x02
#define OREN_HW_LOCK_ENABLED             0x04
#define OREN_LOW_BANK_BITS               0x18
#define OREN_HIGH_BANK_BITS              0x60
#define OREN_KEY_OK                      0x80

/*******************************  DOWNLOAD_CONTROL_REGISTER0 *************************/
#define OREN_SEQ_NUM_BITS                0x1F 

/*******************************  DOWNLOAD_CONTROL_REGISTER1 *************************/
#define OREN_SEQ_CASH_BITS               0x0F

/*******************************    DOWNLOAD_STATUS_REG_1    *************************/
#define OREN_DOWNLOAD_IN_PROGRESS        0x40                 
#define OREN_SEQ_DNLD_ERROR_DEMAND       0x80  /* Sequence error occured when downloading the page sequences page */

/*******************************    DOWNLOAD_STATUS_REG_0    *************************/
#define OREN_DPS0_DOWNLOAD_ERROR_BITS    0x03
#define OREN_DPS0_DOWNLOAD_REDUNDANT     0x01
#define OREN_DPS1_DOWNLOAD_ERROR_BITS    0x0C
#define OREN_DPS1_DOWNLOAD_REDUNDANT     0x04
#define OREN_IPL_DOWNLOAD_ERROR_BITS     0x30
#define OREN_IPL_DOWNLOAD_REDUNDANT      0x10
#define OREN_SEQUENCE_DOWNLOAD_ERROR     0x40
#define OREN_OTP_DOWNLOAD_ERROR          0x80 

/* Allow loading IPL/DPS from redundant copy */
#define OREN_CLEAN_DOWNLOAD              0xEA

/*******************************     FLASH_GEOMETRY_REG_0    **************************/
#define OREN_ROW_ADDR_BYTE_NUM           0x01
#define OREN_PAGE_ADDR_BIT_NUM_BITS      0x0E  
#define OREN_UNIT_ADDR_BIT_NUM_BITS      0xF0

/*******************************     FLASH_GEOMETRY_REG_0    **************************/
#define OREN_PAGE_OFS_ADDR_BIT_NUM_BITS  0x0F
#define OREN_ADDR_BYTE_NUM_BITS          0x70  
#define OREN_PAGE_MAPPING_BIT            0x80


/******************************* Flash Parameters  *****************************/

#define OREN_SECTOR_BCH_PROTECTED  SECTOR_DATA_SIZE+SECTOR_PAGEINFO_SIZE+SECTOR_HM_SIZE
#define OREN_SECTOR_HM_PROTECTED   SECTOR_PAGEINFO_SIZE    


/******************************* Flash Bank interface  *****************************/
#define OREN_ONE_FLASH_8_BITS      0x00      /* Only one 8 bit flash is connected  */
#define OREN_ONE_FLASH_16_BITS     0x01   /* only one 16 bit flash is connected */
#define OREN_TWO_FLASHES_CASCADED  0x02   /* Two 8 bit flashes cascaded         */
#define OREN_TWO_FLASHES_SEPERATED 0x03   /* Two 8 bit flashes connected to the */
                                          /* same bank but the distinction is   */
                                          /* by the BL bit                      */

/*******************************    Flash Status Reg   *****************************/
#define OREN_OPERATION_OK          0x00
#define OREN_OPERATION_FAILED      0x01   
#define OREN_PLANE_0_FAIL          0x02
#define OREN_PLANE_1_FAIL          0x04
#define OREN_PLANE_2_FAIL          0x08
#define OREN_PLANE_3_FAIL          0x10

/*******************************     IRQ FLAGS        *****************************/
#define OREN_NO_IRQ_TRIGGER             0x0
#define OREN_IRQ_ENABLE                 0x1
#define OREN_IRQ_FIFO_ERROR             0x2
#define OREN_IRQ_PROTECTION_ERROR       0x4
#define OREN_IRQ_FREADY_TRIGGER         0x8
#define OREN_IRQ_CLEAR_IRQ_FREADY       0x10
#define OREN_IRQ_CLEAR_IRQ_PROTECTION   0x20
#define OREN_IRQ_CLEAR_IRQ_FIFO         0x40
     
/*******************************     ECC FLAGS         *****************************/
#define OREN_NO_ECC                     0x0
#define OREN_BCH_ENABLE                 0x2
#define OREN_HM_ENABLE                  0x4
#define OREN_AUTO_PARITY                0x8

/*******************************     INTLV_FLAG       *****************************/
#define OREN_INTLV_1_8_BIT              0x01
#define OREN_INTLV_1_16_BIT             0x02    /* Currently not supported */
#define OREN_INTLV_2_CASCADED           0x04    /* Two 8 bits flash are cascaded to create one virtual 16 bit flash */     
#define OREN_INTLV_2_SEPERATED          0x08    /* Two seperate 8 bit flash exists in each bank */

/*******************************     DOWNLOAD FLAGS   *****************************/
#define OREN_COPY_0                     0x0
#define OREN_COPY_1                     0x1
#define OREN_COPY_2                     0x2
#define OREN_COPY_3                     0x3
#define OREN_FIRST_GOOD_COPY            0x10 
#define OREN_ALL_COPIES                 0x20
/*******************************       LPC            *****************************/
#define OREN_LPC_FLASH_DATA_INDEX       0x40

/*******************************    LOCK FLAG         *****************************/
#define OREN_LOCKED                        1
#define OREN_NOT_LOCKED                 0

/*******************************  PROTECTION FLAG     *****************************/
#define OREN_PROTECTED                  1
#define OREN_NOT_PROTECTED              0

/*******************************  CORRUPTION          *****************************/ 
#define OREN_COPY_GOOD                  0x0
#define OREN_COPY_CORRUPTED             0x1

/*******************************  PROTECTION FLAGS    *****************************/ 
#define OREN_NO_PROTECTION              0x0