📄 oren_mtd.h
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/***********************************************************************************/
/* M-Systems Confidential */
/* Copyright (C) M-Systems Flash Disk Pioneers Ltd. 1995-2003 */
/* All Rights Reserved */
/***********************************************************************************/
/* NOTICE OF M-SYSTEMS OEM */
/* SOFTWARE LICENSE AGREEMENT */
/* */
/* THE USE OF THIS SOFTWARE IS GOVERNED BY A SEPARATE LICENSE */
/* AGREEMENT BETWEEN THE OEM AND M-SYSTEMS. REFER TO THAT AGREEMENT */
/* FOR THE SPECIFIC TERMS AND CONDITIONS OF USE, */
/* OR CONTACT M-SYSTEMS FOR LICENSE ASSISTANCE: */
/* E-MAIL = info@m-sys.com */
/***********************************************************************************/
/*
* $Log: V:/PVCSDB/DiskOnChip/archives/general storage/TrueFFS/src/mtd/oren_mtd.h-arc $
*
* Rev 1.5 11 Sep 2003 16:02:48 oris
* Added backward compatability flag FL_XSCALE_BOOT_MODE
*
* Rev 1.4 Sep 01 2003 19:04:02 oris
* - Added 2K page new sequences offset in sequence cache RAM
* - Added 2K page flash commands definitions
* - Added sectorOffset to OREN_OperationsArgsStruct
*
* Rev 1.3 Aug 10 2003 14:40:54 roneng
* - Added 2K page new sequences offset in sequence cache RAM
* - Added 2K page flash commands definitions
* - Added sectorOffset to OREN_OperationsArgsStruct
*
* Rev 1.2 May 12 2003 20:46:48 roneng
* - Change the COTP struct
*
* Rev 1.1 May 06 2003 11:55:24 OriS
* Removed warnings
*
* Rev 1.0 Apr 09 2003 12:15:56 OriS
* Initial revision.
*
*/
/************************************************************************
* Name : mtd_oren.h *
* *
* Written : Ronen Golan *
* *
* Abstract: This file contains the prototypes of the OREN MTD *
************************************************************************/
#ifndef MTD_OREN_H
#define MTD_OREN_H
/*************************** Definitions ****************************/
#define MTD_VARS ((MTDVarsStruct *) flashPtr->mtdVars)
#define MTD_VARS_BUFFER (MTD_VARS->buffer->flData)
/**************************** Typedefs ****************************/
/************************* Run Time Definitions *************************/
#define MAX_BANKS 4
#define FOUNDRY_DATA_SIZE 0x200
#define FOUNDRY_RESERVED_SIZE 8
/************************ Access layer routines *************************/
#ifndef OREN_Write8BitReg
#define OREN_Write8BitReg(flash,offset,val) (flash)->memWrite8bit((flash)->win,offset,val)
#endif
#ifndef OREN_DirectWrite16BitReg
#define OREN_DirectWrite16BitReg(flash,offset,val) (flash)->memWrite16bit((flash)->win,offset,val)
#endif
#ifndef OREN_Read8BitReg
#define OREN_Read8BitReg(flash,offset) (flash)->memRead8bit((flash)->win,offset)
#endif
#ifndef OREN_DirectRead16BitReg
#define OREN_DirectRead16BitReg(flash,offset) (flash)->memRead16bit((flash)->win,offset)
#endif
#ifndef OREN_ReadEvenNumberOfBytes
#define OREN_ReadEvenNumberOfBytes(flash,offset,dest,count) (flash)->memRead((flash)->win,offset,dest,count)
#endif
#ifndef OREN_WriteEvenNumberOfBytes
#define OREN_WriteEvenNumberOfBytes(flash,offset,src,count) (flash)->memWrite((flash)->win,offset,src,count)
#endif
#ifndef OREN_DocWindow
#define OREN_DocWindow(flash) (flash->memWindowSize())
#endif
/************************* Include files *********************/
/*************************** MEMORY MAP **********************/
#define OREN_IPL_AREA_0 0x0000
#define OREN_IPL_AREA_1 0x0400
#define OREN_IPL_AREA_2 0x1800
#define OREN_IPL_AREA_3 0x1c00
#ifndef FL_XSCALE_BOOT_MODE
#define OREN_FLASH_DATA_REG_ALIASED 0x0800
#else /* Do not read from 4 bytes aligned address */
#define OREN_FLASH_DATA_REG_ALIASED 0x0802 /* Prevent access to 32bit alligned address */
#endif /* FL_XSCALE_BOOT_MODE */
#define OREN_MEMORY_MAP_SIZE 0x2000
#define OREN_IPL_CODE_SIZE 0x400L
/************************** Register Address Map ************************/
/************************** DOC CONTROL REGS ************************/
#define OREN_CHIP_ID_REG 0x1000 /* READ */
#define OREN_CHIP_ID_CONFIRM_REG 0x1074 /* READ+WRITE */
#define OREN_NOP_REG 0x1002 /* READ+WRITE */
#define OREN_ALIAS_RESOLUTION_REG 0x1004 /* READ+WRITE */
#define OREN_BUS_LOCK_REGISTER 0x1006 /* READ+WRITE */
#define OREN_BUS_SWAP_REG 0x1008 /* READ+WRITE */
#define OREN_DEVICE_ID_SELECT_REG 0x100A /* READ+WRITE */
#define OREN_DOC_CONTROL_REG 0x100C /* READ+WRITE */
#define OREN_DOC_CONTROL_CONFIRM_REG 0x1072 /* READ+WRITE */
#define OREN_CONFIGURATION_REG 0x100E /* READ+WRITE */
#define OREN_INTERRUPT_CONTROL_REG 0x1010 /* READ+WRITE */
#define OREN_FOUNDRY_TEST_REG 0x1076 /* READ+WRITE */
#define OREN_HW_PROTECTION_CONTROL_REG 0x1012 /* READ+WRITE */
#define OREN_FOUNDRY_KEY_REG 0x1078 /* READ+WRITE */
#define OREN_OUTPUT_CONTROL_REG 0x1014 /* READ+WRITE */
/************************** ICMU REGISTERS **************************/
#define OREN_ICMU_CORRECT_FACTOR_REG 0x1016 /* READ+WRITE */
#define OREN_ICMU_CONTROL_REG 0x1018 /* READ+WRITE */
#define OREN_CLOCK_COUNTER_REG 0x101A /* READ+WRITE */
/************************** LPC REGISTERS **************************/
#define OREN_LPC_CONFIGURATION_REG 0x1020 /* READ+WRITE */
#define OREN_LPC_STRAPPING_REG 0X1022 /* READ */
#define OREN_LPC_DMA_REG 0x1024 /* READ+WRITE */
#define OREN_LPC_INTERRUPT_REG 0x1026 /* READ+WRITE */
#define OREN_LPC_IO_INDEX_REG 0x0007 /* READ+WRITE */
/************************** FLASH REGISTERS **************************/
#define OREN_FLASH_CONTROL_REG 0x1038 /* READ+WRITE */
#define OREN_FLASH_STATUS_REG 0x103A /* READ */
#define OREN_FLASH_ACCESS_CONFIG_REG 0x103E /* READ+WRITE */
#define OREN_FLASH_SEQUENCE_REG 0x1032 /* READ+WRITE */
#define OREN_FLASH_COMMAND_REG 0x1034 /* READ+WRITE */
#define OREN_FLASH_ADDRESS_REG 0x1036 /* READ+WRITE */
#define OREN_FLASH_DATA_REG 0x1030 /* READ+WRITE */
#define OREN_FLASH_DATA_REG_LB_BYTE 0x103C /* READ+WRITE */
/************************** ECC REGISTERS **************************/
#define OREN_FLASH_BCH_PARITY_REG 0x1048 /* READ+WRITE */
#define OREN_HAMMING_PARITY_REG 0x1046 /* READ */
#define OREN_ECC_PRESET_REG 0x1044 /* READ+WRITE */
#define OREN_ECC_CONTROL_REG_0 0x1040 /* READ+WRITE */
#define OREN_ECC_CONTROL_REG_1 0x1042 /* READ+WRITE */
/************************** PROTECTION REGISTERS **************************/
#define OREN_COTP_POINTER_REG 0x1050 /* READ */
#define OREN_COTP_LOCK_POINTER_REG 0x1052 /* READ */
#define OREN_BBT_POINTER_REG 0x1054 /* READ */
#define OREN_PROTECTION_STATUS_REG 0x1056 /* READ */
#define OREN_DPS0_ADDRESS_LOW_REG 0x1060 /* READ */
#define OREN_DPS0_ADDRESS_HIGH_REG 0x1062 /* READ */
#define OREN_DPS1_ADDRESS_LOW_REG 0x1064 /* READ */
#define OREN_DPS1_ADDRESS_HIGH_REG 0x1066 /* READ */
#define OREN_DPS0_POINTER_REG 0x1068 /* READ */
#define OREN_DPS1_POINTER_REG 0x106A /* READ */
#define OREN_DPS0_STATUS_REG 0x106c /* READ */
#define OREN_DPS1_STATUS_REG 0x106e /* READ */
#define OREN_DPS_0_KEY_REG 0x105c /* WRITE */
#define OREN_DPS_1_KEY_REG 0x105e /* WRITE */
#define OREN_FLASH_GEOMETRY_REG_0 0x1058 /* READ */
#define OREN_FLASH_GEOMETRY_REG_1 0x105a /* READ */
/************************** DOWNLOAD REGISTERS **************************/
#define OREN_DOWNLOAD_STATUS_REGISTER0 0x1070 /* READ+WRITE */
#define OREN_SEQUENCE_CASH_RAM_START 0x1100 /* READ+WRITE */
/**************************************************************************/
/**********************************************************************************
***************************** Register Description ***************************
**********************************************************************************/
/******************************* BUS_SWAP_REG *****************************/
#define OREN_SWAP_L 0x0001
#define OREN_SWAP_H 0x0100
#define OREN_SWAP_DATA_BYTES SWAP_H | SWAP_L
/******************************* DOC_CONTROL_REG *****************************/
#define OREN_MODE_BITS 0x03
#define OREN_MODE_WRITE_ENABLE 0x04
#define OREN_BDETCT_RESET 0x08 /* Set whenever the controller entered a reset mode as a result of Boot detector trigger. Cleared by writing 1 */
#define OREN_RSTIN_RESET 0x10 /* Set whenever the controller entered a reset mode as a result of RSTIN# input signal asserted .Cleared by writing 1 */
#define OREN_CLOCK_STOP 0x20
/******************************* CONFIGURATION_REG *****************************/
#define OREN_BUS_CONFIGURATION_BITS 0x03
#define OREN_RAM_WRITE_ENABLE 0x04
#define OREN_RAM_READ_ENABLE 0x08
#define OREN_MAX_ID_BITS 0x30
#define OREN_BOOT_DETECTOR_INHIBIT 0x40
#define OREN_IF_CFG_STATUS 0x80
/******************************* INTERRUPT_CONTROL_REG *************************/
#define OREN_IRQ_ENABLED 0x80
#define OREN_IRQ_FIFO_PENDING 0x40
#define OREN_IRQ_PROTECTION_PENDING 0x20
#define OREN_IRQ_FREADY_PENDING 0x10
#define OREN_IRQ_EDGE_SENSITIVE 0x08
#define OREN_IRQ_ENABLE_FIFO_INT 0x04
#define OREN_IRQ_ENABLE_PROTECTION_INT 0x02
#define OREN_IRQ_ENABLE_FREADY_INT 0x01
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