📄 m512_mtd.h
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/******************************* M512_FIRST_GOOD_UNIT_REG *************************/
#define M512_GOOD_UNIT_WRITE_EN 0x80
#define M512_GOOD_UNIT_NUM_BITS 0x7F
/******************************* FLASH_TYPE *****************************/
#define M512_SLC_TYPE 0x1
#define M512_MLC_TYPE 0x2
#define M512_ERASE_MARK 0xAA
/******************************* M512_DOWNLOAD_STATUS_REG *************************/
#define M512_DPS0_DOWNLOAD_ERROR_BITS 0x03
#define M512_DPS0_DOWNLOAD_REDUNDANT 0x01
#define M512_DPS1_DOWNLOAD_ERROR_BITS 0x0C
#define M512_DPS1_DOWNLOAD_REDUNDANT 0x04
#define M512_IPL_DOWNLOAD_ERROR_BITS 0x30
#define M512_IPL_DOWNLOAD_REDUNDANT 0x10
#define M512_OTP_DOWNLOAD_ERROR 0x40
#define M512_DOWNLOAD_ERROR_BITS 0x4A
#define M512_DOWNLOAD_IN_PROGRESS 0x80
#define M512_DPS_REVISION_NUMBER 0x10
/******************************* ENUMERATIONS **************************/
/******************************* Flash Parameters *****************************/
#define M512_SECTOR_BCH_PROTECTED SECTOR_DATA_SIZE+SECTOR_PAGEINFO_SIZE+SECTOR_HM_SIZE
#define M512_SECTOR_HM_PROTECTED SECTOR_PAGEINFO_SIZE
/******************************* Flash Bank interface *****************************/
#define M512_ONE_FLASH_8_BITS 0x00 /* Only one 8 bit flash is connected */
#define M512_ONE_FLASH_16_BITS 0x01 /* only one 16 bit flash is connected */
#define M512_TWO_FLASHES_CASCADED 0x02 /* Two 8 bit flashes cascaded */
#define M512_TWO_FLASHES_SEPERATED 0x03 /* Two 8 bit flashes connected to the */
/* same bank but the distinction is */
/* by the BL bit */
/******************************* Flash Status Reg *****************************/
#define M512_OPERATION_OK 0x00
#define M512_OPERATION_FAILED 0x01
#define M512_PLANE_0_FAIL 0x02
#define M512_PLANE_1_FAIL 0x04
#define M512_PLANE_2_FAIL 0x08
#define M512_PLANE_3_FAIL 0x10
/******************************* IRQ FLAGS *****************************/
#define M512_NO_IRQ_TRIGGER 0x0
#define M512_IRQ_ENABLE 0x1
#define M512_IRQ_FIFO_ERROR 0x2
#define M512_IRQ_PROTECTION_ERROR 0x4
#define M512_IRQ_FREADY_TRIGGER 0x8
#define M512_IRQ_CLEAR_IRQ_FREADY 0x10
#define M512_IRQ_CLEAR_IRQ_PROTECTION 0x20
#define M512_IRQ_CLEAR_IRQ_FIFO 0x40
/******************************* ECC FLAGS *****************************/
#define M512_NO_ECC 0x0
#define M512_BCH_ENABLE 0x2
#define M512_HM_ENABLE 0x4
#define M512_AUTO_PARITY 0x8
/******************************* INTLV_FLAG *****************************/
#define M512_INTLV_1_8_BIT 0x01
#define M512_INTLV_1_16_BIT 0x02 /* Currently not supported */
#define M512_INTLV_2_CASCADED 0x04 /* Two 8 bits flash are cascaded to create one virtual 16 bit flash */
#define M512_INTLV_2_SEPERATED 0x08 /* Two seperate 8 bit flash exists in each bank */
/******************************* DOWNLOAD FLAGS *****************************/
#define M512_COPY_0 0x0
#define M512_COPY_1 0x1
#define M512_COPY_2 0x2
#define M512_COPY_3 0x3
#define M512_FIRST_GOOD_COPY 0x10
#define M512_ALL_COPIES 0x20
/******************************* LOCK FLAG *****************************/
#define M512_LOCKED 1
#define M512_NOT_LOCKED 0
/******************************* PROTECTION FLAG *****************************/
#define M512_PROTECTED 1
#define M512_NOT_PROTECTED 0
/******************************* CORRUPTION *****************************/
#define M512_COPY_GOOD 0x0
#define M512_COPY_CORRUPTED 0x1
/******************************* PROTECTION FLAGS *****************************/
#define M512_NO_PROTECTION 0x0
#define M512_WP 0x1
#define M512_RP 0x2
#define M512_HW_LOCK 0x4
/******************************* DOWNLOAD FLAGS *****************************/
#define M512_DOWNLOAD_OK 0x0
#define M512_DOWNLOAD_ERROR 0x1
#define M512_DOWNLOAD_MAIN_UNIT_ERROR 0x2
/******************************* ERASE_FLAGS *****************************/
#define M512_WAIT_FOR_READY 0x1
/******************************* Micellencious *****************************/
#define M512_CHIP_ID 0x0200
#define M512_CHIP_ID_COMPLEMENT 0xFDFF
#define M256_CHIP_ID 0x0100
#define M256_CHIP_ID_COMPLEMENT 0xFEFF
#define M1G_CHIP_ID 0x0400
#define M1G_CHIP_ID_COMPLEMENT 0xFBFF
#define M512_KEY_LENGTH 8
#define M512_BUSY_DELAY 30000L
#define M512_PD_DELAY 30000L
#define M512_DOWNLOAD_DELAY 300000L
#define M512_FIFO_DELAY 30000L
#define M512_ICMU_DELAY 30000L
#define M512_ALIAS_RESOLUTION 17
#define M512_UNIQUE_ID_LENGTH 16
#define M512_FOUNDRY_OTP_SIZE 16
#define M512_DEFAULT_START_ADR 0xC8000L
#define M512_DEFAULT_STOP_ADR 0xE0000L
#define M512_OTP_LOCK_MARK 0
#define M512_OTP_START_PAGE 8
#define M512_OTP_LOCK_PAGE 0x3E
#define M512_CUSTOMER_OTP_SIZE 6L*1024L
#define M512_BITS_IN_BYTE 8
#define M512_CHANGEABLE_PROTECTED_AREA 2
#define M512_TOTAL_PROTECTED_AREA 2
#define M512_BBT_BLOCKS_PERPAGE_SHIFT 12
#define M512_BBT_BLOCKS_PERPAGE_MASK 0xfff
#define M512_MLC_BB_PERCENTAGE 5
#define M512_NUM_OF_PLANES 2
#define M512_BBT_PAGE 4
#define M512_DPS_0_MAIN_UNIT 1
#define M512_DPS_0_REDUNDANT_UNIT 2
#define M512_DPS_1_MAIN_UNIT 3
#define M512_DPS_1_REDUNDANT_UNIT 4
#define M512_RAM_READS_TO_EXIT_DPD 12
#define OP_COMPLETED 0x0
#define M512_MLC_BAD_BLOCK_PERCENTAGE 5
#define M512_FOTP_SIZE 0x20
#define M512_PRODUCT_TYPE_LOCATION 2
#define M512_MAX_NUMBER_OF_PLANES 2
/**********************************************************************************/
/*************************** Enumarations ********************************/
typedef enum FL_DPS_IndexEnum
{
DPS_0 = 0,
DPS_1 = 1
} FL_DPS_IndexE ;
typedef enum FL_AsicModeEnum
{
RESET_MODE = 0,
NORMAL_MODE = 1,
POWER_DOWN_MODE = 2
} FL_AsicModeE;
typedef enum FL_EccModeEnum
{
ECC_WRITE_MODE = 0,
ECC_READ_MODE = 1
}FL_EccModeE;
typedef enum FL_IrqTriggerEnum
{
IRQ_PROTECTION ,
IRQ_FREADY ,
IRQ_FIFO_ERROR ,
IRQ_NOT_PENDING
} FL_IrqTriggerE;
typedef enum FL_IrqTypeEnum
{
LEVEL_TYPE_INT = 0,
EDGE_TYPE_INT = 1
} FL_IrqTypeE;
typedef enum FL_BusConfigEnum
{
SRAM_MODE = 0 ,
MUX_MODE = 1 ,
LPC_MODE = 2 ,
ICP_MODE = 3
} FL_BusConfigE;
typedef enum FL_FlashCommandsEnum
{
/*** Read commands ***/
READ_AREA_A_CMD = 0x00,
READ_AREA_C_CMD = 0x50,
MULTI_PLANE_READ = 0x30,
/*** Output commands ***/
READ_STATUS_CMD = 0x70,
READ_STATUS_MULTI_CMD = 0x71,
READ_ID_CMD = 0x90,
ADDR_INPUT_FOR_REG_READ = 0x05,
REG_READ = 0xE0,
/*** Program commands ***/
PAGE_PROG_CYCLE_1_CMD = 0x80,
PAGE_PROG_CYCLE_2_CMD = 0x10,
PAGE_PROG_DUMMY_CMD = 0x11,
/*** Erase commands ***/
BLOCK_ADDRESS_INPUT = 0x60,
PAGE_ERASE_CYCLE_2_CMD = 0xD0,
/*** Other commands ***/
RESET_COMMAND = 0xFF,
/*** Mode commands ***/
SET_PAGE_SIZE_532_BYTES = 0x3C,
SET_FAST_MODE = 0xA2,
SET_RELIABLE_MODE = 0x22,
SET_AUTO_PAGE_INC_ENABLE = 0xB3
}FL_FlashCommandsE ;
typedef enum FL_ResetTriggerEnum
{
BOOT_DETECTOR_TRIGGER,
RSTIN_TRIGGER,
NOT_KNOWN_TRIGGER
} FL_ResetTriggerE ;
typedef enum FL_SequenceID_Enum
{
RESET_SEQ = 0 ,
PAGE_SIZE_532_BYTES_SEQ = 3 ,
SET_FAST_MODE_SEQ = 5 ,
SET_VPGM_LOW_SEQ = 7 ,
SET_RELIABLE_MODE_SEQ = 9 ,
ENABLE_AUTO_PAGE_INC_SEQ = 12,
AREA_A_POINT_SEQ = 14,
AREA_C_POINT_SEQ = 16,
READ_SEQ = 18,
PAGE_PROGRAM_SEQ = 29,
ERASE_SEQ = 39,
STATUS_READ_SEQ = 46,
STATUS_READ_MULTI_PLANE = 49,
READ_ID_SEQ = 52,
PAGE_BUFFER_LOOP_BACK = 68
} FL_SequenceID_E ;
/******************************* STRUCTS ******************************/
typedef struct
{
/************************* Input parameters ********************************/
PhyUnitType *phyUnits ; /*** The actual physical units ***/
FLByte phyPage ; /*** The page that the units reside in ***/
FLWord sectorOffset; /*** Offset when working in RAW mode ***/
FLDword opFlags ; /*** Operation flags ***/
FLByte noOfPhySectors ; /*** Number of physical units to access in parallel ***/
FLByte floor ; /*** The floor ***/
FLByte FAR1 *mainBuffer ; /*** Pointer to the main buffer ***/
FLByte FAR1 *extraBuffer; /*** Pointer to the extra buffer ***/
FLByte verifyWrite ; /*** Verify that write succeeded ***/
/************************* RawMode parameters *******************************/
FLWord offset; /*** Offset when working in RAW mode ***/
FLWord length; /*** Length when working in raw mode ***/
/************************** Output parameters ********************************/
FLSByte maxBitErrors; /*** In verify write option it returns the Max errors in sector read ***/ /* cahr is used because of the EDC code */
FLDword noOfSectorsPassed;/*** Number of sectors that were successfully passed ***/
FLDword freeSectorsFound; /*** Number of free sectors found ***/
/**********************************************************************************/
} M512_OperationArgsStruct ,*M512_OperationArgsStructPtr ;
typedef struct
{
LEushort lowUnit ;
LEushort highUnit ;
FLByte protectionKey[8] ;
FLByte protectionType ;
FLByte fillWithZero[3] ; /* Reserved */
} DPS_Struct ,*DPS_StructPtr ;
typedef struct
{
FLDword LockMark ;
LEulong COTP_Size ;
} customerLockStruct,*customerLockStructPtr ;
typedef struct
{
FLWord wM512_BUS_SWAP_REG_Val ;
FLByte bM512_CONFIGURATION_REG_Val ;
FLByte bM512_INTERRUPT_CONTROL_REG_Val ;
FLByte bM512_OUTPUT_CONTROL_REG_Val ;
FLByte bM512_ECC_CONTROL_REG_1_Val ;
FLByte bM512_DPD_CONTROL_REG ;
FLWord wM512_DMA_CONTROL_REG_0 ;
FLByte bM512_DMA_CONTROL_REG_1 ;
FLByte bM512_BURST_CONTROL_REG ;
} M512_RegSavedVal_S,*M512_RegSavedVal_P ;
#endif /* MTD_M512_H */
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