📄 m512_mtd.h
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/***********************************************************************************/
/* M-Systems Confidential */
/* Copyright (C) M-Systems Flash Disk Pioneers Ltd. 1995-2003 */
/* All Rights Reserved */
/***********************************************************************************/
/* NOTICE OF M-SYSTEMS OEM */
/* SOFTWARE LICENSE AGREEMENT */
/* */
/* THE USE OF THIS SOFTWARE IS GOVERNED BY A SEPARATE LICENSE */
/* AGREEMENT BETWEEN THE OEM AND M-SYSTEMS. REFER TO THAT AGREEMENT */
/* FOR THE SPECIFIC TERMS AND CONDITIONS OF USE, */
/* OR CONTACT M-SYSTEMS FOR LICENSE ASSISTANCE: */
/* E-MAIL = info@m-sys.com */
/***********************************************************************************/
/*
* $Log: V:/PVCSDB/DiskOnChip/archives/general storage/TrueFFS/src/mtd/m512_mtd.h-arc $
*
* Rev 1.5 Jan 27 2004 08:14:00 oris
* Changed comments
*
* Rev 1.4 Sep 21 2003 09:34:14 OriS
* Added backward compatability flag FL_XSCALE_BOOT_MODE
*
* Rev 1.3 May 18 2003 15:32:14 OriS
* Fixed spaces
*
* Rev 1.2 May 12 2003 20:38:20 roneng
* - Change the COTP struct
*
* Rev 1.1 May 06 2003 11:55:58 OriS
* Wrong address for NOP register
*
* Rev 1.0 Apr 09 2003 12:15:54 OriS
* Initial revision.
*
*/
/************************************************************************
* Name : m512_mtd.h *
* *
* Written : Ronen Golan *
* *
* Abstract: This file contains the prototypes of the M512 MTD *
************************************************************************/
#ifndef MTD_M512_H
#define MTD_M512_H
/*************************** Definitions ****************************/
#define MTD_VARS ((MTDVarsStruct *) flashPtr->mtdVars)
#define MTD_VARS_BUFFER (MTD_VARS->buffer->flData)
/**************************** Typedefs ****************************/
/************************* Run Time Definitions *************************/
#define MAX_BANKS 4
#define PAGE_INFO_LENGTH 7
#define BCH_ECC_LENGTH 7
#define HM_ECC_LENGTH 1
#define FOUNDRY_DATA_SIZE 0x200
#define FOUNDRY_RESERVED_SIZE 8
#ifndef M512_Write8BitReg
#define M512_Write8BitReg(flash,offset,val) flash->memWrite8bit (flash->win,offset,val)
#endif
#ifndef M512_DirectWrite16BitReg
#define M512_DirectWrite16BitReg(flash,offset,val) flash->memWrite16bit (flash->win,offset,val)
#endif
#ifndef M512_DirectRead8BitReg
#define M512_DirectRead8BitReg(flash,offset) flash->memRead8bit (flash->win,offset)
#endif
#ifndef M512_DirectRead16BitReg
#define M512_DirectRead16BitReg(flash,offset) flash->memRead16bit (flash->win,offset)
#endif
#ifndef M512_ReadEvenNumberOfBytes
#define M512_ReadEvenNumberOfBytes(flash,offset,dest,count) flash->memRead (flash->win,offset,dest,count)
#endif
#ifndef M512_WriteEvenNumberOfBytes
#define M512_WriteEvenNumberOfBytes(flash,offset,src,count) flash->memWrite (flash->win,offset,src,count)
#endif
#ifndef M512_DocWindow
#define M512_DocWindow(flash) (flash)->memWindowSize()
#endif
/************************* Include files *********************/
/*************************** MEMORY MAP **********************/
#define M512_IPL_AREA_0 0x0000
#define M512_IPL_AREA_1 0x1800
#ifndef FL_XSCALE_BOOT_MODE
#define M512_FLASH_DATA_REG_ALIASED 0x0800
#else /* Do not read from 4 bytes aligned address */
#define M512_FLASH_DATA_REG_ALIASED 0x0802 /* Prevent access to 32bit alligned address */
#endif /* FL_XSCALE_BOOT_MODE */
#define M512_MEMORY_MAP_SIZE 0x2000 /* Size of memory window is - 8K */
#define M512_IPL_CODE_SIZE 0x800 /* IPL size is 2KByte */
/************************** Register Address Map ************************/
/************************** DOC CONTROL REGS ************************/
#define M512_CHIP_ID_REG 0x1000 /* READ */
#define M512_CHIP_ID_CONFIRM_REG 0x1074 /* READ+WRITE */
#define M512_NOP_REG 0x103E /* READ+WRITE */
#define M512_ALIAS_RESOLUTION_REG 0x1004 /* READ+WRITE */
#define M512_BUS_LOCK_REGISTER 0x1006 /* READ+WRITE */
#define M512_BUS_SWAP_REG 0x1008 /* READ+WRITE */
#define M512_DEVICE_ID_SELECT_REG 0x100A /* READ+WRITE */
#define M512_DOC_CONTROL_REG 0x100C /* READ+WRITE */
#define M512_DOC_CONTROL_CONFIRM_REG 0x1072 /* READ+WRITE */
#define M512_CONFIGURATION_REG 0x100E /* READ+WRITE */
#define M512_INTERRUPT_CONTROL_REG 0x1010 /* READ+WRITE */
#define M512_FOUNDRY_TEST_REG 0x1076 /* READ+WRITE */
#define M512_OUTPUT_CONTROL_REG 0x1014 /* READ+WRITE */
#define M512_DPD_CONTROL_REG 0x107C /* READ+WRITE */
#define M512_RTC_ENABLE_REG 0x1016 /* READ+WRITE */
#define M512_RTC_REG 0x1018 /* READ+WRITE */
#define M512_READ_ADDRESS_REG 0x101A /* READ+WRITE */
#define M512_BURST_CONTROL_REG 0x101C /* READ+WRITE */
#define M512_INTERRUPT_STATUS_REG 0x1020 /* READ+WRITE */
#define M512_FIRST_GOOD_UNIT_REG 0x1022 /* READ+WRITE */
#define M512_DMA_CONTROL_REG_0 0x1078 /* READ+WRITE */
#define M512_DMA_CONTROL_REG_1 0x107A /* READ+WRITE */
/************************** FLASH REGISTERS **************************/
#define M512_FLASH_CONTROL_REG 0x1038 /* READ+WRITE */
#define M512_FLASH_SEQUENCE_REG 0x1032 /* READ+WRITE */
#define M512_FLASH_COMMAND_REG 0x1034 /* READ+WRITE */
#define M512_FLASH_ADDRESS_REG 0x1036 /* READ+WRITE */
#define M512_FLASH_DATA_REG 0x1030 /* READ+WRITE */
#define M512_FLASH_END_OF_DATA_REG 0x101E /* READ+WRITE */
/************************** ECC REGISTERS **************************/
#define M512_FLASH_BCH_PARITY_REG 0x1048 /* READ+WRITE */
#define M512_HAMMING_PARITY_REG 0x1046 /* READ */
#define M512_ECC_PRESET_REG 0x1044 /* READ+WRITE */
#define M512_ECC_CONTROL_REG_0 0x1040 /* READ+WRITE */
#define M512_ECC_CONTROL_REG_1 0x1042 /* READ+WRITE */
/************************** PROTECTION REGISTERS **************************/
#define M512_PROTECTION_STATUS_REG 0x1056 /* READ */
#define M512_DPS0_ADDRESS_LOW_REG 0x1060 /* READ */
#define M512_DPS0_ADDRESS_HIGH_REG 0x1062 /* READ */
#define M512_DPS1_ADDRESS_LOW_REG 0x1064 /* READ */
#define M512_DPS1_ADDRESS_HIGH_REG 0x1066 /* READ */
#define M512_DPS0_STATUS_REG 0x106c /* READ */
#define M512_DPS1_STATUS_REG 0x106e /* READ */
#define M512_DPS_0_KEY_REG 0x105c /* WRITE */
#define M512_DPS_1_KEY_REG 0x105e /* WRITE */
/************************** DOWNLOAD REGISTERS **************************/
#define M512_DOWNLOAD_STATUS_REG 0x1070 /* READ+WRITE */
/**************************************************************************/
/**********************************************************************************
***************************** Register Description ***************************
**********************************************************************************/
/***************************** M512_BUS_SWAP_REG **************************/
#define M512_SWAP_L 0x0001
#define M512_SWAP_H 0x0100
#define M512_SWAP_DATA_BYTES SWAP_H | SWAP_L
/***************************** M512_DOC_CONTROL_REG **************************/
#define M512_MODE_BITS 0x03
#define M512_MODE_WRITE_ENABLE 0x04
#define M512_BDETCT_RESET 0x08
#define M512_RSTIN_RESET 0x10
#define M512_RAM_WE 0x20
/***************************** M512_CONFIGURATION_REG **************************/
#define M512_VDET_OUTPUT 0x01
#define M512_BOOT_DETECTOR_INHIBIT 0x08
#define M512_MAX_ID_BITS 0x30
#define M512_IF_CFG_STATUS 0x80
/***************************** M512_INTERRUPT_CONTROL_REG *************************/
#define M512_IRQ_ENABLED 0x8000
#define M512_IRQ_EDGE_SENSITIVE 0x4000
#define M512_IRQ_ENABLE_DMA_INT 0x2000
#define M512_IRQ_ENABLE_RTC_INT 0x1000
#define M512_IRQ_ENABLE_BCH_ECC_INT 0x0800
#define M512_IRQ_ENABLE_DATA_OVF_INT 0x0400
#define M512_IRQ_ENABLE_PROTECTION_INT 0x0200
#define M512_IRQ_ENABLE_FREADY_INT 0x0100
#define M512_IRQ_MASK_DMA_INT 0x0020
#define M512_IRQ_MASK_RTC_INT 0x0010
#define M512_IRQ_MASK_BCH_ECC_INT 0x0008
#define M512_IRQ_MASK_DATA_OVF_INT 0x0004
#define M512_IRQ_MASK_PROTECTION_INT 0x0002
#define M512_IRQ_MASK_FREADY_INT 0x0001
/***************************** M512_INTERRUPT_STATUS_REG *************************/
#define M512_IRQ_DMA_PENDING_INT 0x20
#define M512_IRQ_RTC_PENDING_INT 0x10
#define M512_IRQ_BCH_PENDING_ECC_INT 0x08
#define M512_IRQ_DATA_OVF_PENDING_INT 0x04
#define M512_IRQ_PROTECTION_PENDING_INT 0x02
#define M512_IRQ_FREADY_PENDING_INT 0x01
/***************************** M512_FOUNDRY_TEST_REG *************************/
#define M512_SOFT_RESET 0x80
#define M512_WR_ALL_PIN 0x08
#define M512_TEST_A_MODE 0x04 /* In this mode the boot detector will be incremented by 11H instead of 01H */
#define M512_DOWNLOAD_TEST_MODE 0x02 /* Download test mode - data is downloaded from D[7:0] instead of the flash */
#define M512_FLASH_TEST_MODE 0x01 /* When set provides all the pin signals on the I/O pins */
/***************************** M512_OUTPUT_CONTROL_REG *************************/
#define M512_ASSERT_BUSY_DURING_DNLD 0x01
#define M512_DISABLE_PULL_UP_BITS 0x02
#define M512_TURBO_MODE 0x04
/******************************* M512_DPD_CONTROL_REG *************************/
#define M512_POWER_DOWN_OK 0x80
#define M512_POWER_DOWN_MODE_BITS 0x0F
/******************************* M512_DMA_CONTROL_REG_0 *********************/
#define M512_DMA_ENABLE 0x8000
#define M512_DMA_PAUSE 0x4000
#define M512_DMA_EDGE_MODE 0x2000
#define M512_DMA_DMARQ_POLARITY 0x1000
#define M512_SECTOR_COUNT_BITS 0x007F
/******************************* M512_DMA_CONTROL_REG_1 *********************/
#define M512_NEGATE_COUNT_BITS 0x03FF
/******************************* M512_DMA_CONTROL_REG_1 *********************/
#define M512_NEGATE_COUNT_BITS 0x03FF
/******************************* M512_BURST_MODE_CONTROL_REG *********************/
#define M512_BURST_ENABLE 0x0001
#define M512_BURST_CLOCK_INVERT 0x0002
#define M512_BURST_HOLD 0x0004
#define M512_BURST_LATENCY_BITS 0x0F00
#define M512_BURST_LENGTH_BITS 0xF000
/******************************* M512_CLOCK_COUNTER_REG *********************/
#define M512_CLOCK_COUNTER_RESET 0x8000 /* The counter starts to count from zero */
#define M512_CLOCK_COUNTER_STOP 0x4000 /* The counter is stopped until CLOCK_COUNTER_RESET is set */
#define M512_CLOCK_COUNTER_BITS 0x3FFF
/******************************* M512_READ_ADDRESS_REG *************************/
#define M512_ADDR_INCREMENTED 0x8000
#define M512_ADDR_ACCESS_ONE_BYTE 0x4000
#define M512_ADDR_ADDRESS_BITS 0x1FFF
/******************************* M512_REAL_ADDRESS_REG *************************/
#define M512_ADDR_INCREMENTED 0x8000
#define M512_ADDR_READ_ONE_BYTE 0x4000
#define M512_ADDR_ADDRESS_BITS 0x1FFF
/******************************* M512_RTC_ENABLE_REG *************************/
#define M512_ENABLE_RTC 0x0001
/******************************* M512_FLASH_CONTROL_REG **************************/
#define M512_FWP_SIGNAL_ACTIVE 0x20 /* After protocol violation detected we must clear this bit */
#define M512_FCE_SIGNAL_ACTIVE 0x10 /* Controls the assertion of the CE# to the BANK defined by the BANK bits */
#define M512_SEQ_STATE_MACHINE_READY 0x08
#define M512_PROTECTION_ERROR_DETECTED 0x04 /* Protection Error & will be cleared after FLASH reset command */
#define M512_SEQUENCE_ERROR_DETECTED 0x02 /* Sequence Error detected & will be cleared only by FLASH reset command */
#define M512_FLASH_READY 0x01 /* FLASH READY/BUSY# output signal */
/******************************* M512_ECC_CONTROL_REG_0 ************************/
#define M512_DATA_COUNTER_BITS 0x07FF
#define M512_BCH_EN 0x0800
#define M512_HAMMING_EN 0x1000
#define M512_AUTO_ECC_READ_WRITE_EN 0x4000
#define M512_FLASH_READ_MODE 0x8000 /* Host is doing a read operation */
/******************************* M512_ECC_CONTROL_REG_1 ************************/
#define M512_HM_DATA_NUM_BITS 0x0F
#define M512_PAGE_READ_IS_USED 0x20
#define M512_IGNORE_DATA 0x40
#define M512_BCH_SYNDROM_ERROR 0x80
/****************************** M512_PROTECTION_STATUS_REG *************************/
#define M512_FOUNDRY_OTP_LOCKED 0x01
#define M512_CUSTOMER_OTP_LOCKED 0x02
#define M512_LOCK_INPUT_NEGATED 0x04
#define M512_STICKY_LOCK_ACTIVATED 0x08
#define M512_PROTECTION_ENABLED 0x10
#define M512_DONT_DOWNLOAD_IPL 0x20
#define M512_PROTECTION_ERROR 0x80
/******************************* DPS0_STATUS_REG *************************/
#define M512_OTP_PROTECTED 0x01
#define M512_READ_PROTECTED 0x02
#define M512_WRITE_PROTECTED 0x04
#define M512_HW_LOCK_ENABLED 0x08
#define M512_KEY_OK 0x80
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