boot_cch.asm

TI dm642的汇编ASM测试试验代码

            .title  "Flash bootup utility for DM642 EVM"
            .option D,T
            .length 102
            .width  140
            
COPY_TABLE_TWO  .equ   0x90200000
FLASH_PAGE_FLAG  .equ   0x7
FLASH_Flag_VAL_ADDRONE   .equ   0x90070000
FLASH_Flag_VAL_ADDRTWO   .equ   0x90070008
FLASH_Flag_VAL_ONE .equ   0x2
FLASH_Flag_VAL_TWO .equ   0x1f0000
FLASH_PAGE_TEMP .equ   0xffff

COPY_TABLE  .equ    0x90000400
EMIF_BASE   .equ    0x01800000
FLASH_PAGE_CS	.equ	0x90080400
FLASH_SECOND_PAGE	.equ	0x90080000
FLASH_PAGE_SIZE	.equ	0x80000
;hy_add 20080811
LEDCTLR   .equ  0x01b00000
LEDCTLR1  .equ  0x01b00004
LEDCTLR2  .equ  0x01b00008
GPIO14_1  .equ	0x4000
GPIO14_0  .equ	0xffffbfff
;hy_addend 20080811
            .sect ".boot_load"
            .global _boot
;FLAG      .int 0,1
_boot:      
;************************************************************************
;* Debug Loop -  Comment out B for Normal Operation
;************************************************************************
            zero B1
_myloop:  ; [!B1] B _myloop  
            nop  5
_myloopend: nop


;************************************************************************
;* Configure EMIF
;************************************************************************

        mvkl  emif_values, a3  ; load pointer to emif values
        mvkh  emif_values, a3
        
        mvkl  EMIF_BASE, a4    ; load EMIF base address
        mvkh  EMIF_BASE, a4

        mvkl  0x0009, b0       ; load number of registers to set
        mvkh  0x0000, b0

emif_loop:
        ldw   *a3++, b5        ; load register value
        sub   b0,1,b0          ; decrement counter

        nop   2

 [ b0]  b     emif_loop
        stw   b5, *a4++        ; store register value
        nop   4 
;************************************************************************
;* Configure GPIO14
;************************************************************************ 
;hy_add 20080811  

		mvkl	GPIO14_1,a26
		mvkh	GPIO14_1,a26
		mvkl	GPIO14_0,a25
		mvkh	GPIO14_0,a25
      	mvkl    LEDCTLR,a1
       	mvkh    LEDCTLR,a1
       	ldw    *a1,b1
		nop		4;
       	or     a26,b1,b1
		nop    4; 
       	stw    b1,*a1;初始化GPIO 14
       	nop    4
       	mvkl   LEDCTLR1,a1
      	mvkh   LEDCTLR1,a1
        ldw    *a1,b1
		nop	4
      	or     a26,b1,b1
		nop    4; 
       	stw    b1,*a1;初始化 GPIO 14 为out
       	nop    4
		mvkl   LEDCTLR2,a1
    	mvkh   LEDCTLR2,a1
    	ldw    *a1,b1
		nop	4
		or     a26,b1,b1
    	nop    4;   
    	stw    b1,*a1;给GPIO 14 =1
    	nop    8

;hy_addend 20080811        
;****************************************************************************
;* memory select 
;****************************************************************************
		zero	a14
 		mvkl   FLASH_PAGE_CS,a1
    	mvkh   FLASH_PAGE_CS,a1
 		mvkl   FLASH_PAGE_FLAG,a14
    	mvkh   FLASH_PAGE_FLAG,a14
 		mvkl   FLASH_Flag_VAL_TWO,a23
    	mvkh   FLASH_Flag_VAL_TWO,a23
		nop	5
		stb	a14,*a1
		stb	a14,*a1
		nop	5
    	nop    5    
    	mvkl   FLASH_Flag_VAL_ADDRONE,a1
    	mvkh   FLASH_Flag_VAL_ADDRONE,a1
    	ldw    *a1,b1
    	nop	5
    	mvkl   FLASH_Flag_VAL_ADDRTWO,a20
    	mvkh   FLASH_Flag_VAL_ADDRTWO,a20
    	ldw    *a20,b2
    	nop	5
;		sub   b1,1,b1
		sub   b2,a23,b2
		or    b1,b2,b1
		sub   b1,2,b1
		nop	5
	[b1]	mvkl  COPY_TABLE, a3   ; load table pointer
    [b1]    mvkh  COPY_TABLE, a3
   	[!b1]	mvkl  COPY_TABLE_TWO, a3   ; load table pointer
    [!b1]    mvkh  COPY_TABLE_TWO, a3 
    ;*****************************************************************
;* Copy code sections
;****************************************************************************
 ;       mvkl  COPY_TABLE, a3   ; load table pointer
  ;      mvkh  COPY_TABLE, a3
        mvkl  FLASH_PAGE_SIZE, a12   ; load table pointer
        mvkh  FLASH_PAGE_SIZE, a12
		mvkl	FLASH_PAGE_CS,a10
		mvkh	FLASH_PAGE_CS,a10
		mvkl	FLASH_SECOND_PAGE,a11
		mvkh	FLASH_SECOND_PAGE,a11

		zero	a14
	[!b1] add  4,a14,a14
		nop	5
		stb	a14,*a10
		stb	a14,*a10
		nop	5
		nop	5			
        ldw   *a3++, b1        ; Load entry point
		nop	5
		
        zero  a0
copy_section_top:
;hy_add 20080811

	mvkl   LEDCTLR2,a1
    mvkh   LEDCTLR2,a1
    ldw    *a1,b11
    nop    4
  [!a0]	and   a25,b11,b11
  [a0]	or    a26,b11,b11
	nop    4
    stw    b11,*a1 
    nop    4
  ||[a0]	zero  a0
  ||[!a0]	add  1,a0,a0
;hy_addend 20080811
        ldw   *a3++, b0        ; byte count
        nop	5 
        ldw   *a3++, a4        ; ram start address
        nop   5

 [!b0]  b copy_done            ; have we copied all sections?
        nop   5
		
copy_loop:
		cmpltu	a3,a11,a2;a11=0x90080000,a13=result

		nop	5

 ||[a2]	b cch_copy
 ||[!a2]	add	a14,1,a14
		stb	a14,*a10
		sub a3,a12,a3

		nop	5

cch_copy:
;		nop	5
        ldb   *a3++,b5
;        nop	5
;        stb	b5,*a4++
;        nop	5
        sub   b0,1,b0          ; decrement counter
;        nop	5

 [ b0]  b     copy_loop        ; setup branch if not done
 [!b0]  b     copy_section_top
; 		nop	5

        zero  a1
 [!b0]  and   3,a3,a1
        stb   b5,*a4++
 [!b0]  and   -4,a3,a5         ; round address up to next multiple of 4
 [ a1]  add   4,a5,a3          ; round address up to next multiple of 4

;****************************************************************************
;* Jump to entry point
;****************************************************************************
copy_done:
		zero	a14
		nop	5
		stb	a14,*a10
		stb	a14,*a10
		nop	5
		nop	5	
        b    .S2 b1
        nop   5
        nop	5
        nop	5
        nop	5
        nop	5

emif_values:
        .long 0x00052078      ; GBLCTL
;cchchg080201
        .long 0x73a28e01      ; CECTL1 (Flash/FPGA)
;        .long 0x73afbf07      ; CECTL1 (cchchg max time of flash access)
;cchchgend
        .long 0xffffffd3      ; CECTL0 (SDRAM)
        .long 0x00000000      ; Reserved
        .long 0x22a28a22      ; CECTL2
        .long 0x22a28a22      ; CECTL3
        .long 0x57115000      ; SDCTL
        .long 0x0000081b      ; SDTIM (refresh period)
        .long 0x001faf4d      ; SDEXT