📄 hal_uart.lst
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\ 000018 F0 MOVX @DPTR,A
\ 000019 22 RET
\ In segment BANKED_CODE, align 1, keep-with-next
\ ?Subroutine17:
\ 000000 F0 MOVX @DPTR,A
\ 000001 8E82 MOV DPL,R6
\ 000003 8F83 MOV DPH,R7
\ 000005 A3 INC DPTR
\ 000006 22 RET
\ In segment BANKED_CODE, align 1, keep-with-next
\ ?Subroutine8:
\ 000000 E0 MOVX A,@DPTR
\ 000001 90.... MOV DPTR,#(dmaCh1234 + 29)
\ 000004 F0 MOVX @DPTR,A
\ 000005 90.... MOV DPTR,#(dmaCh1234 + 28)
\ 000008 E0 MOVX A,@DPTR
\ 000009 54E0 ANL A,#0xe0
\ 00000B F0 MOVX @DPTR,A
\ 00000C 53D1EF ANL 0xd1,#0xef
\ 00000F 75D610 MOV 0xd6,#0x10
\ 000012 22 RET
\ In segment BANKED_CODE, align 1, keep-with-next
\ ?Subroutine1:
\ 000000 A3 INC DPTR
\ 000001 A3 INC DPTR
\ 000002 A3 INC DPTR
\ 000003 A3 INC DPTR
\ 000004 E0 MOVX A,@DPTR
\ 000005 F8 MOV R0,A
\ 000006 74D0 MOV A,#-0x30
\ 000008 28 ADD A,R0
\ 000009 F8 MOV R0,A
\ 00000A 74FF MOV A,#-0x1
\ 00000C 3400 ADDC A,#0x0
\ 00000E F9 MOV R1,A
\ 00000F C3 CLR C
\ 000010 EA MOV A,R2
\ 000011 98 SUBB A,R0
\ 000012 E4 CLR A
\ 000013 99 SUBB A,R1
\ 000014 A2D2 MOV C,0xD0 /* PSW */.2
\ 000016 65D0 XRL A,PSW
\ 000018 33 RLC A
\ 000019 22 RET
\ In segment BANKED_CODE, align 1, keep-with-next
\ ?Subroutine5:
\ 000000 EE MOV A,R6
\ 000001 240F ADD A,#0xf
\ ??Subroutine5_0:
\ 000003 F582 MOV DPL,A
\ 000005 EF MOV A,R7
\ ??Subroutine5_1:
\ 000006 12.... LCALL ?Subroutine18 & 0xFFFF
\ ??CrossCallReturnLabel_63:
\ 000009 22 RET
\ In segment BANKED_CODE, align 1, keep-with-next
\ ?Subroutine18:
\ 000000 3400 ADDC A,#0x0
\ 000002 F583 MOV DPH,A
\ 000004 E0 MOVX A,@DPTR
\ 000005 22 RET
371 #endif
372
373 #if HAL_UART_ISR
374 /******************************************************************************
375 * @fn pollISR
376 *
377 * @brief Poll a USART module implemented by ISR.
378 *
379 * @param cfg - USART configuration structure.
380 *
381 * @return none
382 *****************************************************************************/
383 static void pollISR( uartCfg_t *cfg )
384 {
385 uint8 cnt = UART_RX_AVAIL( cfg );
386
387 if ( !(cfg->flag & UART_CFG_RXF) )
388 {
389 // If anything received, reset the Rx idle timer.
390 if ( cfg->rxCnt != cnt )
391 {
392 cfg->rxTick = HAL_UART_RX_IDLE;
393 cfg->rxCnt = cnt;
394 }
395
396 /* It is necessary to stop Rx flow in advance of a full Rx buffer because
397 * bytes can keep coming while sending H/W fifo flushes.
398 */
399 if ( cfg->rxCnt >= (cfg->rxMax - SAFE_RX_MIN) )
400 {
401 RX_STOP_FLOW( cfg );
402 }
403 }
404 }
405 #endif
406
407 /******************************************************************************
408 * @fn HalUARTInit
409 *
410 * @brief Initialize the UART
411 *
412 * @param none
413 *
414 * @return none
415 *****************************************************************************/
\ In segment BANKED_CODE, align 1, keep-with-next
416 void HalUARTInit( void )
\ HalUARTInit:
417 {
\ 000000 C082 PUSH DPL
\ 000002 C083 PUSH DPH
\ 000004 ; Saved register size: 2
\ 000004 ; Auto size: 0
418 #if HAL_UART_DMA
419 halDMADesc_t *ch;
420 #endif
421
422 // Set P2 priority - USART0 over USART1 if both are defined.
423 P2DIR &= ~P2DIR_PRIPO;
\ 000004 53FF3F ANL 0xff,#0x3f
\ 000007 E5FF MOV A,0xff
424 P2DIR |= HAL_UART_PRIPO;
\ 000009 85FFFF MOV 0xff,0xff
425
426 #if HAL_UART_0_ENABLE
427 // Set UART0 I/O location to P0.
428 PERCFG &= ~HAL_UART_0_PERCFG_BIT;
\ 00000C 53F1FE ANL 0xf1,#0xfe
429
430 /* Enable Tx and Rx on P0 */
431 P0SEL |= HAL_UART_0_P0_RX_TX;
\ 00000F 43F30C ORL 0xf3,#0xc
\ 000012 E5F3 MOV A,0xf3
432
433 /* Make sure ADC doesnt use this */
434 ADCCFG &= ~HAL_UART_0_P0_RX_TX;
\ 000014 53F2F3 ANL 0xf2,#0xf3
\ 000017 E5F2 MOV A,0xf2
435
436 /* Mode is UART Mode */
437 U0CSR = CSR_MODE;
\ 000019 758680 MOV 0x86,#-0x80
438
439 /* Flush it */
440 U0UCR = UCR_FLUSH;
\ 00001C 75C480 MOV 0xc4,#-0x80
441 #endif
442
443 #if HAL_UART_1_ENABLE
444 // Set UART1 I/O location to P1.
445 PERCFG |= HAL_UART_1_PERCFG_BIT;
446
447 /* Enable Tx and Rx on P1 */
448 P1SEL |= HAL_UART_1_P1_RX_TX;
449
450 /* Make sure ADC doesnt use this */
451 ADCCFG &= ~HAL_UART_1_P1_RX_TX;
452
453 /* Mode is UART Mode */
454 U1CSR = CSR_MODE;
455
456 /* Flush it */
457 U1UCR = UCR_FLUSH;
458 #endif
459
460 #if HAL_UART_DMA
461 // Setup Tx by DMA.
462 ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX );
463
464 // The start address of the destination.
465 HAL_DMA_SET_DEST( ch, DMA_UDBUF );
\ 00001F 74DF MOV A,#-0x21
\ 000021 90.... MOV DPTR,#(dmaCh1234 + 18)
\ 000024 F0 MOVX @DPTR,A
\ 000025 74C1 MOV A,#-0x3f
\ 000027 90.... MOV DPTR,#(dmaCh1234 + 19)
\ 00002A F0 MOVX @DPTR,A
466
467 // Using the length field to determine how many bytes to transfer.
468 HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN );
\ 00002B 90.... MOV DPTR,#(dmaCh1234 + 20)
\ 00002E E0 MOVX A,@DPTR
\ 00002F 541F ANL A,#0x1f
\ 000031 F0 MOVX @DPTR,A
469
470 // One byte is transferred each time.
471 HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE );
472
473 // The bytes are transferred 1-by-1 on Tx Complete trigger.
474 HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE );
475 HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_TX );
\ 000032 740F MOV A,#0xf
\ 000034 90.... MOV DPTR,#(dmaCh1234 + 22)
\ 000037 F0 MOVX @DPTR,A
476
477 // The source address is decremented by 1 byte after each transfer.
478 HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 );
479
480 // The destination address is constant - the Tx Data Buffer.
481 HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 );
482
483 // The DMA is to be polled and shall not issue an IRQ upon completion.
484 HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE );
485
486 // Xfer all 8 bits of a byte xfer.
487 HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS );
488
489 // DMA Tx has shared priority for memory access - every other one.
490 HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH );
\ 000038 7442 MOV A,#0x42
\ 00003A 90.... MOV DPTR,#(dmaCh1234 + 23)
\ 00003D F0 MOVX @DPTR,A
491
492 // Setup Rx by DMA.
493 ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX );
494
495 // The start address of the source.
496 HAL_DMA_SET_SOURCE( ch, DMA_UDBUF );
\ 00003E 74DF MOV A,#-0x21
\ 000040 90.... MOV DPTR,#(dmaCh1234 + 24)
\ 000043 F0 MOVX @DPTR,A
\ 000044 74C1 MOV A,#-0x3f
\ 000046 90.... MOV DPTR,#(dmaCh1234 + 25)
\ 000049 F0 MOVX @DPTR,A
497
498 // Using the length field to determine how many bytes to transfer.
499 HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN );
\ 00004A 90.... MOV DPTR,#(dmaCh1234 + 28)
\ 00004D E0 MOVX A,@DPTR
\ 00004E 541F ANL A,#0x1f
\ 000050 F0 MOVX @DPTR,A
500
501 /* The trick is to cfg DMA to xfer 2 bytes for every 1 byte of Rx.
502 * The byte after the Rx Data Buffer is the Baud Cfg Register,
503 * which always has a known value. So init Rx buffer to inverse of that
504 * known value. DMA word xfer will flip the bytes, so every valid Rx byte
505 * in the Rx buffer will be preceded by a DMA_PAD char equal to the
506 * Baud Cfg Register value.
507 */
508 HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_WORD );
509
510 // The bytes are transferred 1-by-1 on Rx Complete trigger.
511 HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE );
512 HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_RX );
\ 000051 748E MOV A,#-0x72
\ 000053 90.... MOV DPTR,#(dmaCh1234 + 30)
\ 000056 F0 MOVX @DPTR,A
513
514 // The source address is constant - the Rx Data Buffer.
515 HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 );
516
517 // The destination address is incremented by 1 word after each transfer.
518 HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 );
519
520 // The DMA is to be polled and shall not issue an IRQ upon completion.
521 HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE );
522
523 // Xfer all 8 bits of a byte xfer.
524 HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS );
525
526 // DMA has highest priority for memory access.
527 HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH );
\ 000057 7412 MOV A,⌨️ 快捷键说明
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