drx3973d_map.h

用于DRX3973或DRX39系列的芯片的控制

#define SC_RA_RAM_IR_COARSE_2K_KAISINC__W               16
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M               0xFFFF
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE             0x100



#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A                0x8200D4    
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W                16
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M                0xFFFF
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE              0x8
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A               0x8200D5    
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__W               16
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__M               0xFFFF
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE             0x8
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A               0x8200D6    
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__W               16
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M               0xFFFF
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE             0x200





#define SC_RA_RAM_IR_FINE_2K_LENGTH__A                  0x8200D7    
#define SC_RA_RAM_IR_FINE_2K_LENGTH__W                  16
#define SC_RA_RAM_IR_FINE_2K_LENGTH__M                  0xFFFF
#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE                0x9
#define SC_RA_RAM_IR_FINE_2K_FREQINC__A                 0x8200D8    
#define SC_RA_RAM_IR_FINE_2K_FREQINC__W                 16
#define SC_RA_RAM_IR_FINE_2K_FREQINC__M                 0xFFFF
#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE               0x4
#define SC_RA_RAM_IR_FINE_2K_KAISINC__A                 0x8200D9    
#define SC_RA_RAM_IR_FINE_2K_KAISINC__W                 16
#define SC_RA_RAM_IR_FINE_2K_KAISINC__M                 0xFFFF
#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE               0x100



#define SC_RA_RAM_IR_FINE_8K_LENGTH__A                  0x8200DA    
#define SC_RA_RAM_IR_FINE_8K_LENGTH__W                  16
#define SC_RA_RAM_IR_FINE_8K_LENGTH__M                  0xFFFF
#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE                0xB
#define SC_RA_RAM_IR_FINE_8K_FREQINC__A                 0x8200DB    
#define SC_RA_RAM_IR_FINE_8K_FREQINC__W                 16
#define SC_RA_RAM_IR_FINE_8K_FREQINC__M                 0xFFFF
#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE               0x1
#define SC_RA_RAM_IR_FINE_8K_KAISINC__A                 0x8200DC    
#define SC_RA_RAM_IR_FINE_8K_KAISINC__W                 16
#define SC_RA_RAM_IR_FINE_8K_KAISINC__M                 0xFFFF
#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE               0x40



#define SC_RA_RAM_ECHO_SHIFT_LIM__A                     0x8200DD    
#define SC_RA_RAM_ECHO_SHIFT_LIM__W                     16
#define SC_RA_RAM_ECHO_SHIFT_LIM__M                     0xFFFF
#define SC_RA_RAM_ECHO_SHIFT_LIM__PRE                   0xFFFF
#define SC_RA_RAM_ECHO_AGE__A                           0x8200DE    
#define SC_RA_RAM_ECHO_AGE__W                           16
#define SC_RA_RAM_ECHO_AGE__M                           0xFFFF
#define SC_RA_RAM_ECHO_AGE__PRE                         0xFFFF
#define SC_RA_RAM_ECHO_FILTER__A                        0x8200DF    
#define SC_RA_RAM_ECHO_FILTER__W                        16
#define SC_RA_RAM_ECHO_FILTER__M                        0xFFFF
#define SC_RA_RAM_ECHO_FILTER__PRE                      0x2





#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A                0x8200E0    
#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W                16
#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M                0xFFFF
#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE              0x7
#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A               0x8200E1    
#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W               16
#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M               0xFFFF
#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE             0x1
#define SC_RA_RAM_NI_INIT_2K_POS_LR__A                  0x8200E2    
#define SC_RA_RAM_NI_INIT_2K_POS_LR__W                  16
#define SC_RA_RAM_NI_INIT_2K_POS_LR__M                  0xFFFF
#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE                0xE8



#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A                0x8200E3    
#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W                16
#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M                0xFFFF
#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE              0xE
#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A               0x8200E4    
#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W               16
#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M               0xFFFF
#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE             0x7
#define SC_RA_RAM_NI_INIT_8K_POS_LR__A                  0x8200E5    
#define SC_RA_RAM_NI_INIT_8K_POS_LR__W                  16
#define SC_RA_RAM_NI_INIT_8K_POS_LR__M                  0xFFFF
#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE                0xA0



#define SC_RA_RAM_SAMPLE_RATE_COUNT__A                  0x8200E8    
#define SC_RA_RAM_SAMPLE_RATE_COUNT__W                  16
#define SC_RA_RAM_SAMPLE_RATE_COUNT__M                  0xFFFF
#define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE                0x10
#define SC_RA_RAM_SAMPLE_RATE_STEP__A                   0x8200E9    
#define SC_RA_RAM_SAMPLE_RATE_STEP__W                   16
#define SC_RA_RAM_SAMPLE_RATE_STEP__M                   0xFFFF
#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE                 0x113



#define SC_RA_RAM_TPS_TIMEOUT_LIM__A                    0x8200EA    
#define SC_RA_RAM_TPS_TIMEOUT_LIM__W                    16
#define SC_RA_RAM_TPS_TIMEOUT_LIM__M                    0xFFFF
#define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE                  0xC8
#define SC_RA_RAM_TPS_TIMEOUT__A                        0x8200EB    
#define SC_RA_RAM_TPS_TIMEOUT__W                        16
#define SC_RA_RAM_TPS_TIMEOUT__M                        0xFFFF
#define SC_RA_RAM_REG__AX                               0x8200F0    
#define SC_RA_RAM_REG__XSZ                              2
#define SC_RA_RAM_REG__W                                16
#define SC_RA_RAM_REG__M                                0xFFFF
#define SC_RA_RAM_BREAK__A                              0x8200F2    
#define SC_RA_RAM_BREAK__W                              16
#define SC_RA_RAM_BREAK__M                              0xFFFF
#define SC_RA_RAM_BOOTCOUNT__A                          0x8200F3    
#define SC_RA_RAM_BOOTCOUNT__W                          16
#define SC_RA_RAM_BOOTCOUNT__M                          0xFFFF



#define SC_RA_RAM_LC_ABS_2K__A                          0x8200F4    
#define SC_RA_RAM_LC_ABS_2K__W                          16
#define SC_RA_RAM_LC_ABS_2K__M                          0xFFFF
#define SC_RA_RAM_LC_ABS_2K__PRE                        0x1F
#define SC_RA_RAM_LC_ABS_8K__A                          0x8200F5    
#define SC_RA_RAM_LC_ABS_8K__W                          16
#define SC_RA_RAM_LC_ABS_8K__M                          0xFFFF
#define SC_RA_RAM_LC_ABS_8K__PRE                        0x1F





#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A            0x8200F6    
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W            16
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M            0xFFFF
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE          0x1
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A            0x8200F7    
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W            16
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M            0xFFFF
#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE          0x0



#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A             0x8200F8    
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W             16
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M             0xFFFF
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE           0x3
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A             0x8200F9    
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W             16
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M             0xFFFF
#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE           0x2
#define SC_RA_RAM_STACKUNDERFLOW__A                     0x8200FF    
#define SC_RA_RAM_STACKUNDERFLOW__W                     16
#define SC_RA_RAM_STACKUNDERFLOW__M                     0xFFFF





#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A             0x8201A0    
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W             16
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M             0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE           0x1D6
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A             0x8201A1    
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W             16
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M             0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE           0x4



#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A                0x8201A2    
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W                16
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M                0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE              0x1BB
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A                0x8201A3    
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W                16
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M                0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE              0x5



#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A               0x8201A4    
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W               16
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M               0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE             0x1EF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A               0x8201A5    
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W               16
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M               0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE             0x5



#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A            0x8201A6    
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W            16
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M            0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE          0x15E
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A            0x8201A7    
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W            16
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M            0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE          0x5



#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A            0x8201A8    
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W            16
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M            0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE          0x11A
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A            0x8201A9    
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W            16
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M            0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE          0x6



#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A               0x8201AA    
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W               16
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M               0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE             0x1FB
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A               0x8201AB    
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W               16
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M               0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE             0x5



#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A            0x8201AC    
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W            16
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M            0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE          0x12F
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A            0x8201AD    
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W            16
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M            0xFFFF
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE          0x5



#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A            0x8201AE    
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W            16
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M            0xFFFF
#de