📄 drx3973d_map.h
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#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4
#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8
#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC
#define SC_RA_RAM_OP_PARAM_CONST__B 4
#define SC_RA_RAM_OP_PARAM_CONST__W 2
#define SC_RA_RAM_OP_PARAM_CONST__M 0x30
#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
#define SC_RA_RAM_OP_PARAM_HIER__B 6
#define SC_RA_RAM_OP_PARAM_HIER__W 3
#define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0
#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0
#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40
#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80
#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
#define SC_RA_RAM_OP_PARAM_RATE__B 9
#define SC_RA_RAM_OP_PARAM_RATE__W 3
#define SC_RA_RAM_OP_PARAM_RATE__M 0xE00
#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
#define SC_RA_RAM_OP_PARAM_PRIO__B 12
#define SC_RA_RAM_OP_PARAM_PRIO__W 1
#define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000
#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
#define SC_RA_RAM_OP_AUTO__A 0x820049
#define SC_RA_RAM_OP_AUTO__W 6
#define SC_RA_RAM_OP_AUTO__M 0x3F
#define SC_RA_RAM_OP_AUTO__PRE 0x1F
#define SC_RA_RAM_OP_AUTO_MODE__B 0
#define SC_RA_RAM_OP_AUTO_MODE__W 1
#define SC_RA_RAM_OP_AUTO_MODE__M 0x1
#define SC_RA_RAM_OP_AUTO_GUARD__B 1
#define SC_RA_RAM_OP_AUTO_GUARD__W 1
#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2
#define SC_RA_RAM_OP_AUTO_CONST__B 2
#define SC_RA_RAM_OP_AUTO_CONST__W 1
#define SC_RA_RAM_OP_AUTO_CONST__M 0x4
#define SC_RA_RAM_OP_AUTO_HIER__B 3
#define SC_RA_RAM_OP_AUTO_HIER__W 1
#define SC_RA_RAM_OP_AUTO_HIER__M 0x8
#define SC_RA_RAM_OP_AUTO_RATE__B 4
#define SC_RA_RAM_OP_AUTO_RATE__W 1
#define SC_RA_RAM_OP_AUTO_RATE__M 0x10
#define SC_RA_RAM_OP_AUTO_PRIO__B 5
#define SC_RA_RAM_OP_AUTO_PRIO__W 1
#define SC_RA_RAM_OP_AUTO_PRIO__M 0x20
#define SC_RA_RAM_PILOT_STATUS__A 0x82004A
#define SC_RA_RAM_PILOT_STATUS__W 16
#define SC_RA_RAM_PILOT_STATUS__M 0xFFFF
#define SC_RA_RAM_PILOT_STATUS_OK 0x0
#define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1
#define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2
#define SC_RA_RAM_LOCK__A 0x82004B
#define SC_RA_RAM_LOCK__W 4
#define SC_RA_RAM_LOCK__M 0xF
#define SC_RA_RAM_LOCK_DEMOD__B 0
#define SC_RA_RAM_LOCK_DEMOD__W 1
#define SC_RA_RAM_LOCK_DEMOD__M 0x1
#define SC_RA_RAM_LOCK_FEC__B 1
#define SC_RA_RAM_LOCK_FEC__W 1
#define SC_RA_RAM_LOCK_FEC__M 0x2
#define SC_RA_RAM_LOCK_MPEG__B 2
#define SC_RA_RAM_LOCK_MPEG__W 1
#define SC_RA_RAM_LOCK_MPEG__M 0x4
#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C
#define SC_RA_RAM_BE_OPT_ENA__W 3
#define SC_RA_RAM_BE_OPT_ENA__M 0x7
#define SC_RA_RAM_BE_OPT_ENA__PRE 0x5
#define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0
#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
#define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2
#define SC_RA_RAM_BE_OPT_ENA_MAX 0x3
#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
#define SC_RA_RAM_BE_OPT_DELAY__W 16
#define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF
#define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200
#define SC_RA_RAM_ECHO_THRES__A 0x82004E
#define SC_RA_RAM_ECHO_THRES__W 16
#define SC_RA_RAM_ECHO_THRES__M 0xFFFF
#define SC_RA_RAM_ECHO_THRES__PRE 0x77
#define SC_RA_RAM_CONFIG__A 0x820050
#define SC_RA_RAM_CONFIG__W 16
#define SC_RA_RAM_CONFIG__M 0xFFFF
#define SC_RA_RAM_CONFIG__PRE 0x14
#define SC_RA_RAM_CONFIG_ID__B 0
#define SC_RA_RAM_CONFIG_ID__W 1
#define SC_RA_RAM_CONFIG_ID__M 0x1
#define SC_RA_RAM_CONFIG_ID_PRO 0x0
#define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1
#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1
#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1
#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2
#define SC_RA_RAM_CONFIG_FR_ENABLE__B 2
#define SC_RA_RAM_CONFIG_FR_ENABLE__W 1
#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
#define SC_RA_RAM_CONFIG_MIXMODE__B 3
#define SC_RA_RAM_CONFIG_MIXMODE__W 1
#define SC_RA_RAM_CONFIG_MIXMODE__M 0x8
#define SC_RA_RAM_CONFIG_FREQSCAN__B 4
#define SC_RA_RAM_CONFIG_FREQSCAN__W 1
#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
#define SC_RA_RAM_CONFIG_SLAVE__B 5
#define SC_RA_RAM_CONFIG_SLAVE__W 1
#define SC_RA_RAM_CONFIG_SLAVE__M 0x20
#define SC_RA_RAM_CONFIG_FAR_OFF__B 6
#define SC_RA_RAM_CONFIG_FAR_OFF__W 1
#define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40
#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7
#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1
#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80
#define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8
#define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1
#define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100
#define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15
#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1
#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000
#define SC_RA_RAM_FE_FD_THRES_MIN__A 0x820051
#define SC_RA_RAM_FE_FD_THRES_MIN__W 16
#define SC_RA_RAM_FE_FD_THRES_MIN__M 0xFFFF
#define SC_RA_RAM_FE_FD_THRES_MIN__PRE 0x1F4
#define SC_RA_RAM_FE_FD_THRES_MAX__A 0x820052
#define SC_RA_RAM_FE_FD_THRES_MAX__W 16
#define SC_RA_RAM_FE_FD_THRES_MAX__M 0xFFFF
#define SC_RA_RAM_FE_FD_THRES_MAX__PRE 0x7D0
#define SC_RA_RAM_FE_CF_THRES_MIN__A 0x820053
#define SC_RA_RAM_FE_CF_THRES_MIN__W 16
#define SC_RA_RAM_FE_CF_THRES_MIN__M 0xFFFF
#define SC_RA_RAM_FE_CF_THRES_MIN__PRE 0x1F4
#define SC_RA_RAM_FE_CF_THRES_MAX__A 0x820054
#define SC_RA_RAM_FE_CF_THRES_MAX__W 16
#define SC_RA_RAM_FE_CF_THRES_MAX__M 0xFFFF
#define SC_RA_RAM_FE_CF_THRES_MAX__PRE 0x7D0
#define SC_RA_RAM_CO_THRES_8K__A 0x820055
#define SC_RA_RAM_CO_THRES_8K__W 16
#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF
#define SC_RA_RAM_CO_THRES_8K__PRE 0x10E
#define SC_RA_RAM_CO_THRES_2K__A 0x820056
#define SC_RA_RAM_CO_THRES_2K__W 16
#define SC_RA_RAM_CO_THRES_2K__M 0xFFFF
#define SC_RA_RAM_CO_THRES_2K__PRE 0x208
#define SC_RA_RAM_CO_LEVEL__A 0x820057
#define SC_RA_RAM_CO_LEVEL__W 16
#define SC_RA_RAM_CO_LEVEL__M 0xFFFF
#define SC_RA_RAM_CO_DETECT__A 0x820058
#define SC_RA_RAM_CO_DETECT__W 16
#define SC_RA_RAM_CO_DETECT__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059
#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16
#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB
#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A
#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16
#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB
#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B
#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16
#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB
#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C
#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16
#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD
#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D
#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16
#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED
#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E
#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16
#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF
#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD
#define SC_RA_RAM_MOTION_OFFSET__A 0x82005F
#define SC_RA_RAM_MOTION_OFFSET__W 16
#define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF
#define SC_RA_RAM_MOTION_OFFSET__PRE 0x2
#define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060
#define SC_RA_RAM_STATE_PROC_STOP__XSZ 12
#define SC_RA_RAM_STATE_PROC_STOP__W 16
#define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF
#define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE
#define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4
#define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0
#define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE
#define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE
#define SC_RA_RAM_STATE_PROC_START__AX 0x820070
#define SC_RA_RAM_STATE_PROC_START__XSZ 12
#define SC_RA_RAM_STATE_PROC_START__W 16
#define SC_RA_RAM_STATE_PROC_START__M 0xFFFF
#define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80
#define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2
#define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4
#define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4
#define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4
#define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0
#define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10
#define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0
#define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0
#define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30
#define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0
#define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0
#define SC_RA_RAM_TIMER__A 0x820080
#define SC_RA_RAM_TIMER__W 16
#define SC_RA_RAM_TIMER__M 0xFFFF
#define SC_RA_RAM_FI_OFFSET__A 0x820081
#define SC_RA_RAM_FI_OFFSET__W 16
#define SC_RA_RAM_FI_OFFSET__M 0xFFFF
#define SC_RA_RAM_ECHO_GUARD__A 0x820082
#define SC_RA_RAM_ECHO_GUARD__W 16
#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF
#define SC_RA_RAM_ECHO_GUARD_END__A 0x820083
#define SC_RA_RAM_ECHO_GUARD_END__W 16
#define SC_RA_RAM_ECHO_GUARD_END__M 0xFFFF
#define SC_RA_RAM_IR_FREQ__A 0x8200D0
#define SC_RA_RAM_IR_FREQ__W 16
#define SC_RA_RAM_IR_FREQ__M 0xFFFF
#define SC_RA_RAM_IR_FREQ__PRE 0x0
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
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