📄 drx3973d_map.h
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#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034
#define HI_RA_RAM_SRV_TRM_DAD__W 16
#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF
#define HI_RA_RAM_USR_BEGIN__A 0x420040
#define HI_RA_RAM_USR_BEGIN__W 16
#define HI_RA_RAM_USR_BEGIN__M 0xFFFF
#define HI_RA_RAM_USR_END__A 0x42007F
#define HI_RA_RAM_USR_END__W 16
#define HI_RA_RAM_USR_END__M 0xFFFF
#define HI_IF_RAM_TRP_BPT0__AX 0x430000
#define HI_IF_RAM_TRP_BPT0__XSZ 2
#define HI_IF_RAM_TRP_BPT0__W 12
#define HI_IF_RAM_TRP_BPT0__M 0xFFF
#define HI_IF_RAM_TRP_STKU__AX 0x430002
#define HI_IF_RAM_TRP_STKU__XSZ 2
#define HI_IF_RAM_TRP_STKU__W 12
#define HI_IF_RAM_TRP_STKU__M 0xFFF
#define HI_IF_RAM_USR_BEGIN__A 0x430200
#define HI_IF_RAM_USR_BEGIN__W 12
#define HI_IF_RAM_USR_BEGIN__M 0xFFF
#define HI_IF_RAM_USR_END__A 0x4303FF
#define HI_IF_RAM_USR_END__W 12
#define HI_IF_RAM_USR_END__M 0xFFF
#define SC_SID 0x11
#define SC_COMM_EXEC__A 0x800000
#define SC_COMM_EXEC__W 3
#define SC_COMM_EXEC__M 0x7
#define SC_COMM_EXEC_CTL__B 0
#define SC_COMM_EXEC_CTL__W 3
#define SC_COMM_EXEC_CTL__M 0x7
#define SC_COMM_EXEC_CTL_STOP 0x0
#define SC_COMM_EXEC_CTL_ACTIVE 0x1
#define SC_COMM_EXEC_CTL_HOLD 0x2
#define SC_COMM_EXEC_CTL_STEP 0x3
#define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4
#define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
#define SC_COMM_STATE__A 0x800001
#define SC_COMM_STATE__W 16
#define SC_COMM_STATE__M 0xFFFF
#define SC_COMM_MB__A 0x800002
#define SC_COMM_MB__W 16
#define SC_COMM_MB__M 0xFFFF
#define SC_COMM_SERVICE0__A 0x800003
#define SC_COMM_SERVICE0__W 16
#define SC_COMM_SERVICE0__M 0xFFFF
#define SC_COMM_SERVICE1__A 0x800004
#define SC_COMM_SERVICE1__W 16
#define SC_COMM_SERVICE1__M 0xFFFF
#define SC_COMM_INT_STA__A 0x800007
#define SC_COMM_INT_STA__W 16
#define SC_COMM_INT_STA__M 0xFFFF
#define SC_COMM_INT_MSK__A 0x800008
#define SC_COMM_INT_MSK__W 16
#define SC_COMM_INT_MSK__M 0xFFFF
#define SC_CT_REG_COMM_EXEC__A 0x810000
#define SC_CT_REG_COMM_EXEC__W 3
#define SC_CT_REG_COMM_EXEC__M 0x7
#define SC_CT_REG_COMM_EXEC_CTL__B 0
#define SC_CT_REG_COMM_EXEC_CTL__W 3
#define SC_CT_REG_COMM_EXEC_CTL__M 0x7
#define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0
#define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3
#define SC_CT_REG_COMM_STATE__A 0x810001
#define SC_CT_REG_COMM_STATE__W 10
#define SC_CT_REG_COMM_STATE__M 0x3FF
#define SC_CT_REG_COMM_SERVICE0__A 0x810003
#define SC_CT_REG_COMM_SERVICE0__W 16
#define SC_CT_REG_COMM_SERVICE0__M 0xFFFF
#define SC_CT_REG_COMM_SERVICE1__A 0x810004
#define SC_CT_REG_COMM_SERVICE1__W 16
#define SC_CT_REG_COMM_SERVICE1__M 0xFFFF
#define SC_CT_REG_COMM_SERVICE1_SC__B 1
#define SC_CT_REG_COMM_SERVICE1_SC__W 1
#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2
#define SC_CT_REG_COMM_INT_STA__A 0x810007
#define SC_CT_REG_COMM_INT_STA__W 1
#define SC_CT_REG_COMM_INT_STA__M 0x1
#define SC_CT_REG_COMM_INT_STA_REQUEST__B 0
#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1
#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
#define SC_CT_REG_COMM_INT_MSK__A 0x810008
#define SC_CT_REG_COMM_INT_MSK__W 1
#define SC_CT_REG_COMM_INT_MSK__M 0x1
#define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0
#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1
#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
#define SC_CT_REG_CTL_STK__AX 0x810010
#define SC_CT_REG_CTL_STK__XSZ 4
#define SC_CT_REG_CTL_STK__W 10
#define SC_CT_REG_CTL_STK__M 0x3FF
#define SC_CT_REG_CTL_BPT_IDX__A 0x81001F
#define SC_CT_REG_CTL_BPT_IDX__W 1
#define SC_CT_REG_CTL_BPT_IDX__M 0x1
#define SC_CT_REG_CTL_BPT__A 0x810020
#define SC_CT_REG_CTL_BPT__W 10
#define SC_CT_REG_CTL_BPT__M 0x3FF
#define SC_RA_RAM_PARAM0__A 0x820040
#define SC_RA_RAM_PARAM0__W 16
#define SC_RA_RAM_PARAM0__M 0xFFFF
#define SC_RA_RAM_PARAM1__A 0x820041
#define SC_RA_RAM_PARAM1__W 16
#define SC_RA_RAM_PARAM1__M 0xFFFF
#define SC_RA_RAM_CMD_ADDR__A 0x820042
#define SC_RA_RAM_CMD_ADDR__W 16
#define SC_RA_RAM_CMD_ADDR__M 0xFFFF
#define SC_RA_RAM_CMD__A 0x820043
#define SC_RA_RAM_CMD__W 16
#define SC_RA_RAM_CMD__M 0xFFFF
#define SC_RA_RAM_CMD_NULL 0x0
#define SC_RA_RAM_CMD_PROC_START 0x1
#define SC_RA_RAM_CMD_PROC_TRIGGER 0x2
#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
#define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5
#define SC_RA_RAM_CMD_USER_IO 0x6
#define SC_RA_RAM_CMD_SET_TIMER 0x7
#define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
#define SC_RA_RAM_CMD_MAX 0x8
#define SC_RA_RAM_CMDBLOCK__C 0x4
#define SC_RA_RAM_PROC_ACTIVATE__A 0x820044
#define SC_RA_RAM_PROC_ACTIVATE__W 16
#define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF
#define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFBF
#define SC_RA_RAM_PROC_TERMINATED__A 0x820045
#define SC_RA_RAM_PROC_TERMINATED__W 16
#define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF
#define SC_RA_RAM_SW_EVENT__A 0x820046
#define SC_RA_RAM_SW_EVENT__W 14
#define SC_RA_RAM_SW_EVENT__M 0x3FFF
#define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0
#define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1
#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
#define SC_RA_RAM_SW_EVENT_RUN__B 1
#define SC_RA_RAM_SW_EVENT_RUN__W 1
#define SC_RA_RAM_SW_EVENT_RUN__M 0x2
#define SC_RA_RAM_SW_EVENT_TERMINATE__B 2
#define SC_RA_RAM_SW_EVENT_TERMINATE__W 1
#define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4
#define SC_RA_RAM_SW_EVENT_FT_START__B 3
#define SC_RA_RAM_SW_EVENT_FT_START__W 1
#define SC_RA_RAM_SW_EVENT_FT_START__M 0x8
#define SC_RA_RAM_SW_EVENT_FI_START__B 4
#define SC_RA_RAM_SW_EVENT_FI_START__W 1
#define SC_RA_RAM_SW_EVENT_FI_START__M 0x10
#define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5
#define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1
#define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20
#define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6
#define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1
#define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40
#define SC_RA_RAM_SW_EVENT_CE_IR__B 7
#define SC_RA_RAM_SW_EVENT_CE_IR__W 1
#define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80
#define SC_RA_RAM_SW_EVENT_FE_FD__B 8
#define SC_RA_RAM_SW_EVENT_FE_FD__W 1
#define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100
#define SC_RA_RAM_SW_EVENT_FE_CF__B 9
#define SC_RA_RAM_SW_EVENT_FE_CF__W 1
#define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200
#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10
#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1
#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400
#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11
#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1
#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800
#define SC_RA_RAM_LOCKTRACK__A 0x820047
#define SC_RA_RAM_LOCKTRACK__W 16
#define SC_RA_RAM_LOCKTRACK__M 0xFFFF
#define SC_RA_RAM_LOCKTRACK_NULL 0x0
#define SC_RA_RAM_LOCKTRACK_MIN 0x1
#define SC_RA_RAM_LOCKTRACK_RESET 0x1
#define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2
#define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3
#define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4
#define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5
#define SC_RA_RAM_LOCKTRACK_LC 0x6
#define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7
#define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8
#define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9
#define SC_RA_RAM_LOCKTRACK_TRACK 0xA
#define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB
#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC
#define SC_RA_RAM_LOCKTRACK_MAX 0xD
#define SC_RA_RAM_OP_PARAM__A 0x820048
#define SC_RA_RAM_OP_PARAM__W 13
#define SC_RA_RAM_OP_PARAM__M 0x1FFF
#define SC_RA_RAM_OP_PARAM_MODE__B 0
#define SC_RA_RAM_OP_PARAM_MODE__W 2
#define SC_RA_RAM_OP_PARAM_MODE__M 0x3
#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0
#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1
#define SC_RA_RAM_OP_PARAM_GUARD__B 2
#define SC_RA_RAM_OP_PARAM_GUARD__W 2
#define SC_RA_RAM_OP_PARAM_GUARD__M 0xC
#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0
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