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📄 drx3973d_map.h

📁 用于DRX3973或DRX39系列的芯片的控制
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/* 
 *******************************************************************************************************************
 * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
 * 
 * Filename:            drx3973d_map.h
 * Generated on:        Tue Dec 13 19:50:05 2005
 * Generated by:        IDF:x 1.2.27
 * Generated from:      drx3973d_map
 * Output start:        [entry point]
 * 
 * filename             last modified               re-use  
 * ---------------------------------------------------------
 * drx3973d_map.1.tmp   Tue Dec 13 19:50:04 2005    -       
 * 
 * $(c) 2005 Micronas GmbH. All rights reserved.
 * 
 * This software and related documentation (the 'Software') are intellectual property owned by Micronas and are 
 * copyright of Micronas, unless specifically noted otherwise.
 * 
 * Any use of the Software is permitted only pursuant to the terms of the license agreement, if any, which 
 * accompanies, is included with or applicable to the Software ('License Agreement') or upon express written 
 * consent of Micronas. Any copying, reproduction or redistribution of the Software in whole or in part by any 
 * means not in accordance with the License Agreement or as agreed in writing by Micronas is expressly prohibited.
 * 
 * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE LICENSE AGREEMENT. EXCEPT AS WARRANTED 
 * IN THE LICENSE AGREEMENT THE SOFTWARE IS DELIVERED 'AS IS' AND MICRONAS HEREBY DISCLAIMS ALL WARRANTIES AND 
 * CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, 
 * FITNESS FOR A PARTICULAR PURPOSE, QUIT ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL 
 * PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO USE THE SOFTWARE.
 * 
 * IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, SPECIAL OR OTHER DAMAGES 
 * WHATSOEVER INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF 
 * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE INABILITY TO USE THE 
 * SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH 
 * RESULTING FROM MICRONAS' NEGLIGENCE. $
 * 
 *******************************************************************************************************************
 */

#ifndef __DRX3973D_MAP__H__
#define __DRX3973D_MAP__H__ INCLUDED

#ifdef __cplusplus
extern "C" {
#endif

#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drx3973d_map[];
extern RegisterTableInfo_t drx3973d_map_info[];
#endif 
                                                                                                                    





#define HI_SID                                          0x10        





#define HI_COMM_EXEC__A                                 0x400000    
#define HI_COMM_EXEC__W                                 3
#define HI_COMM_EXEC__M                                 0x7
#define   HI_COMM_EXEC_CTL__B                           0           
#define   HI_COMM_EXEC_CTL__W                           3
#define   HI_COMM_EXEC_CTL__M                           0x7
#define     HI_COMM_EXEC_CTL_STOP                       0x0         
#define     HI_COMM_EXEC_CTL_ACTIVE                     0x1         
#define     HI_COMM_EXEC_CTL_HOLD                       0x2         
#define     HI_COMM_EXEC_CTL_STEP                       0x3         
#define     HI_COMM_EXEC_CTL_BYPASS_STOP                0x4         
#define     HI_COMM_EXEC_CTL_BYPASS_HOLD                0x6         

#define HI_COMM_STATE__A                                0x400001    
#define HI_COMM_STATE__W                                16
#define HI_COMM_STATE__M                                0xFFFF
#define HI_COMM_MB__A                                   0x400002    
#define HI_COMM_MB__W                                   16
#define HI_COMM_MB__M                                   0xFFFF
#define HI_COMM_SERVICE0__A                             0x400003    
#define HI_COMM_SERVICE0__W                             16
#define HI_COMM_SERVICE0__M                             0xFFFF
#define HI_COMM_SERVICE1__A                             0x400004    
#define HI_COMM_SERVICE1__W                             16
#define HI_COMM_SERVICE1__M                             0xFFFF
#define HI_COMM_INT_STA__A                              0x400007    
#define HI_COMM_INT_STA__W                              16
#define HI_COMM_INT_STA__M                              0xFFFF
#define HI_COMM_INT_MSK__A                              0x400008    
#define HI_COMM_INT_MSK__W                              16
#define HI_COMM_INT_MSK__M                              0xFFFF






#define HI_CT_REG_COMM_EXEC__A                          0x410000    
#define HI_CT_REG_COMM_EXEC__W                          3
#define HI_CT_REG_COMM_EXEC__M                          0x7
#define   HI_CT_REG_COMM_EXEC_CTL__B                    0           
#define   HI_CT_REG_COMM_EXEC_CTL__W                    3
#define   HI_CT_REG_COMM_EXEC_CTL__M                    0x7
#define     HI_CT_REG_COMM_EXEC_CTL_STOP                0x0         
#define     HI_CT_REG_COMM_EXEC_CTL_ACTIVE              0x1         
#define     HI_CT_REG_COMM_EXEC_CTL_HOLD                0x2         
#define     HI_CT_REG_COMM_EXEC_CTL_STEP                0x3         


#define HI_CT_REG_COMM_STATE__A                         0x410001    
#define HI_CT_REG_COMM_STATE__W                         10
#define HI_CT_REG_COMM_STATE__M                         0x3FF
#define HI_CT_REG_COMM_SERVICE0__A                      0x410003    
#define HI_CT_REG_COMM_SERVICE0__W                      16
#define HI_CT_REG_COMM_SERVICE0__M                      0xFFFF
#define HI_CT_REG_COMM_SERVICE1__A                      0x410004    
#define HI_CT_REG_COMM_SERVICE1__W                      16
#define HI_CT_REG_COMM_SERVICE1__M                      0xFFFF
#define   HI_CT_REG_COMM_SERVICE1_HI__B                 0           
#define   HI_CT_REG_COMM_SERVICE1_HI__W                 1
#define   HI_CT_REG_COMM_SERVICE1_HI__M                 0x1


#define HI_CT_REG_COMM_INT_STA__A                       0x410007    
#define HI_CT_REG_COMM_INT_STA__W                       1
#define HI_CT_REG_COMM_INT_STA__M                       0x1
#define   HI_CT_REG_COMM_INT_STA_REQUEST__B             0           
#define   HI_CT_REG_COMM_INT_STA_REQUEST__W             1
#define   HI_CT_REG_COMM_INT_STA_REQUEST__M             0x1


#define HI_CT_REG_COMM_INT_MSK__A                       0x410008    
#define HI_CT_REG_COMM_INT_MSK__W                       1
#define HI_CT_REG_COMM_INT_MSK__M                       0x1
#define   HI_CT_REG_COMM_INT_MSK_REQUEST__B             0           
#define   HI_CT_REG_COMM_INT_MSK_REQUEST__W             1
#define   HI_CT_REG_COMM_INT_MSK_REQUEST__M             0x1




#define HI_CT_REG_CTL_STK__AX                           0x410010    
#define HI_CT_REG_CTL_STK__XSZ                          4
#define HI_CT_REG_CTL_STK__W                            10
#define HI_CT_REG_CTL_STK__M                            0x3FF

#define HI_CT_REG_CTL_BPT_IDX__A                        0x41001F    
#define HI_CT_REG_CTL_BPT_IDX__W                        1
#define HI_CT_REG_CTL_BPT_IDX__M                        0x1

#define HI_CT_REG_CTL_BPT__A                            0x410020    
#define HI_CT_REG_CTL_BPT__W                            10
#define HI_CT_REG_CTL_BPT__M                            0x3FF






#define HI_RA_RAM_SLV0_FLG_SMM__A                       0x420010    
#define HI_RA_RAM_SLV0_FLG_SMM__W                       1
#define HI_RA_RAM_SLV0_FLG_SMM__M                       0x1
#define   HI_RA_RAM_SLV0_FLG_SMM_MULTI                  0x0         
#define   HI_RA_RAM_SLV0_FLG_SMM_SINGLE                 0x1         


#define HI_RA_RAM_SLV0_DEV_ID__A                        0x420011    
#define HI_RA_RAM_SLV0_DEV_ID__W                        7
#define HI_RA_RAM_SLV0_DEV_ID__M                        0x7F

#define HI_RA_RAM_SLV0_FLG_CRC__A                       0x420012    
#define HI_RA_RAM_SLV0_FLG_CRC__W                       1
#define HI_RA_RAM_SLV0_FLG_CRC__M                       0x1
#define   HI_RA_RAM_SLV0_FLG_CRC_CONTINUE               0x0         
#define   HI_RA_RAM_SLV0_FLG_CRC_RESTART                0x1         


#define HI_RA_RAM_SLV0_FLG_ACC__A                       0x420013    
#define HI_RA_RAM_SLV0_FLG_ACC__W                       3
#define HI_RA_RAM_SLV0_FLG_ACC__M                       0x7
#define   HI_RA_RAM_SLV0_FLG_ACC_RWM__B                 0           
#define   HI_RA_RAM_SLV0_FLG_ACC_RWM__W                 2
#define   HI_RA_RAM_SLV0_FLG_ACC_RWM__M                 0x3
#define     HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL           0x0         
#define     HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE       0x3         
#define   HI_RA_RAM_SLV0_FLG_ACC_BRC__B                 2           
#define   HI_RA_RAM_SLV0_FLG_ACC_BRC__W                 1
#define   HI_RA_RAM_SLV0_FLG_ACC_BRC__M                 0x4
#define     HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL           0x0         
#define     HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST        0x4         


#define HI_RA_RAM_SLV0_STATE__A                         0x420014    
#define HI_RA_RAM_SLV0_STATE__W                         1
#define HI_RA_RAM_SLV0_STATE__M                         0x1
#define   HI_RA_RAM_SLV0_STATE_ADDRESS                  0x0         
#define   HI_RA_RAM_SLV0_STATE_DATA                     0x1         


#define HI_RA_RAM_SLV0_BLK_BNK__A                       0x420015    
#define HI_RA_RAM_SLV0_BLK_BNK__W                       12
#define HI_RA_RAM_SLV0_BLK_BNK__M                       0xFFF
#define   HI_RA_RAM_SLV0_BLK_BNK_BNK__B                 0           
#define   HI_RA_RAM_SLV0_BLK_BNK_BNK__W                 6
#define   HI_RA_RAM_SLV0_BLK_BNK_BNK__M                 0x3F
#define   HI_RA_RAM_SLV0_BLK_BNK_BLK__B                 6           
#define   HI_RA_RAM_SLV0_BLK_BNK_BLK__W                 6
#define   HI_RA_RAM_SLV0_BLK_BNK_BLK__M                 0xFC0


#define HI_RA_RAM_SLV0_ADDR__A                          0x420016    
#define HI_RA_RAM_SLV0_ADDR__W                          16
#define HI_RA_RAM_SLV0_ADDR__M                          0xFFFF

#define HI_RA_RAM_SLV0_CRC__A                           0x420017    
#define HI_RA_RAM_SLV0_CRC__W                           16
#define HI_RA_RAM_SLV0_CRC__M                           0xFFFF

#define HI_RA_RAM_SLV0_READBACK__A                      0x420018    
#define HI_RA_RAM_SLV0_READBACK__W                      16
#define HI_RA_RAM_SLV0_READBACK__M                      0xFFFF




#define HI_RA_RAM_SLV1_FLG_SMM__A                       0x420020    
#define HI_RA_RAM_SLV1_FLG_SMM__W                       1
#define HI_RA_RAM_SLV1_FLG_SMM__M                       0x1
#define   HI_RA_RAM_SLV1_FLG_SMM_MULTI                  0x0         
#define   HI_RA_RAM_SLV1_FLG_SMM_SINGLE                 0x1         


#define HI_RA_RAM_SLV1_DEV_ID__A                        0x420021    
#define HI_RA_RAM_SLV1_DEV_ID__W                        7
#define HI_RA_RAM_SLV1_DEV_ID__M                        0x7F

#define HI_RA_RAM_SLV1_FLG_CRC__A                       0x420022    
#define HI_RA_RAM_SLV1_FLG_CRC__W                       1
#define HI_RA_RAM_SLV1_FLG_CRC__M                       0x1
#define   HI_RA_RAM_SLV1_FLG_CRC_CONTINUE               0x0         
#define   HI_RA_RAM_SLV1_FLG_CRC_RESTART                0x1         


#define HI_RA_RAM_SLV1_FLG_ACC__A                       0x420023    
#define HI_RA_RAM_SLV1_FLG_ACC__W                       3
#define HI_RA_RAM_SLV1_FLG_ACC__M                       0x7
#define   HI_RA_RAM_SLV1_FLG_ACC_RWM__B                 0           
#define   HI_RA_RAM_SLV1_FLG_ACC_RWM__W                 2
#define   HI_RA_RAM_SLV1_FLG_ACC_RWM__M                 0x3
#define     HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL           0x0         
#define     HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE       0x3         
#define   HI_RA_RAM_SLV1_FLG_ACC_BRC__B                 2           

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