📄 drx3973d.c
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WR16( devAddr, CE_REG_TI_NEXP_OFFS__A ,0x0000, 0x0000);
WR16( devAddr, CE_REG_COMM_EXEC__A ,0x0001, 0x0000); /* start ce */
#endif /* DRXD_TYPE_A */
#if (DRXD_TYPE_B)
devAddr = demod -> myI2CDevAddr;
WR16( devAddr, CE_REG_TI_PHN_ENABLE__A ,0x0001, 0x0000);
WR16( devAddr, CE_REG_FR_PM_SET__A ,0x000D, 0x0000);
WR16( devAddr, CE_REG_COMM_EXEC__A ,0x0001, 0x0000); /* start ce */
#endif /* DRXD_TYPE_B */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
/**
* \fn DRXStatus_t InitEQ( const pDRXDemodInstance_t demod )
* \brief
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitEQ( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
#if (DRXD_TYPE_A)
static u8_t resetData1[] =
{ 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */
0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */
0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */
0x02,0x00 /* EQ_REG_OT_CSI_OFFSET__A */
};
devAddr = demod -> myI2CDevAddr;
WRBLOCK( devAddr, EQ_REG_OT_QNT_THRES0__A , sizeof(resetData1), resetData1 );
WR16( devAddr, EQ_REG_TD_REQ_SMB_CNT__A ,0x0200, 0x0000);
WR16( devAddr, EQ_REG_IS_CLIP_EXP__A ,0x001F, 0x0000);
WR16( devAddr, EQ_REG_SN_OFFSET__A ,-7 , 0x0000);
WR16( devAddr, EQ_REG_RC_SEL_CAR__A ,0x0002, 0x0000);
WR16( devAddr, EQ_REG_COMM_EXEC__A ,0x0001, 0x0000);
#endif /* DRXD_TYPE_A */
#if (DRXD_TYPE_B)
devAddr = demod -> myI2CDevAddr;
WR16( devAddr, EQ_REG_COMM_EXEC__A ,0x0001, 0x0000);
#endif /* DRXD_TYPE_B */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
/**
* \fn DRXStatus_t InitEC( const pDRXDemodInstance_t demod )
* \brief
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitEC( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
pDRX3973DData_t extAttr=NULL;
#if (DRXD_TYPE_A)
static u8_t resetData1[] =
{ 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */
0x1E,0x00, /* EC_SB_REG_CSI_LO__A */
0x01,0x00, /* EC_SB_REG_SMB_TGL__A */
0x7F,0x00, /* EC_SB_REG_SNR_HI__A */
0x7F,0x00, /* EC_SB_REG_SNR_MID__A */
0x7F,0x00 /* EC_SB_REG_SNR_LO__A */
};
static u8_t resetData2[] =
{ 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
(EC_RS_REG_VAL_PCK&0xFF),(EC_RS_REG_VAL_PCK>>8)
/* EC_RS_REG_VAL__A */
};
static u8_t resetData3[] =
{ 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
0x03,0x00 /* EC_OC_REG_TMD_CUR_CNT__A */
};
static u8_t resetData4[] =
{ 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
0x02,0x00 /* EC_OC_REG_AVR_BSH_CNT__A */
};
static u8_t resetData5[] =
{ 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */
0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */
0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */
0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */
0x0A,0x00 /* EC_OC_REG_RCN_GAI_LVL__A */
};
static u8_t resetData6[] =
{ 0xFF,0xFF, /* EC_OC_REG_RCN_CLP_LOP__A */
0xFF,0x00 /* EC_OC_REG_RCN_CLP_HIP__A */
};
devAddr = demod -> myI2CDevAddr;
extAttr = (pDRX3973DData_t) demod -> myExtAttr;
WRBLOCK( devAddr, EC_SB_REG_CSI_HI__A , sizeof(resetData1), resetData1 );
WRBLOCK( devAddr, EC_RS_REG_REQ_PCK_CNT__A , sizeof(resetData2), resetData2 );
WRBLOCK( devAddr, EC_OC_REG_TMD_TOP_MODE__A , sizeof(resetData3), resetData3 );
WRBLOCK( devAddr, EC_OC_REG_AVR_ASH_CNT__A , sizeof(resetData4), resetData4 );
WRBLOCK( devAddr, EC_OC_REG_RCN_MODE__A , sizeof(resetData5), resetData5 );
WRBLOCK( devAddr, EC_OC_REG_RCN_CLP_LOP__A , sizeof(resetData6), resetData6 );
WR16( devAddr, EC_SB_REG_CSI_OFS__A , 0x0001, 0x0000);
WR16( devAddr, EC_VD_REG_FORCE__A , 0x0002, 0x0000);
WR16( devAddr, EC_VD_REG_REQ_SMB_CNT__A , 0x0001, 0x0000);
WR16( devAddr, EC_VD_REG_RLK_ENA__A , 0x0001, 0x0000);
WR16( devAddr, EC_OD_REG_SYNC__A , 0x0664 , 0x0000);
WR16( devAddr, EC_OC_REG_OC_MON_SIO__A , 0x0000, 0x0000);
WR16( devAddr, EC_OC_REG_SNC_ISC_LVL__A , 0x0422, 0x0000);
if ( (extAttr->consumerDevice) == TRUE )
{
/* Output zero on monitorbus pads, power saving */
WR16( devAddr, EC_OC_REG_OCR_MON_UOS__A ,
( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ), 0x0000);
WR16( devAddr, EC_OC_REG_OCR_MON_WRI__A,
EC_OC_REG_OCR_MON_WRI_INIT, 0x0000);
}
WR16( devAddr, EC_SB_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, EC_VD_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, EC_OD_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, EC_RS_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, EC_OC_REG_COMM_EXEC__A , 0x0001, 0x0000);
#endif /* DRXD_TYPE_A */
#if (DRXD_TYPE_B)
devAddr = demod -> myI2CDevAddr;
extAttr = (pDRX3973DData_t) demod -> myExtAttr;
WR16( devAddr, EC_SB_REG_CSI_OFS0__A ,0x0001 , 0x0000);
WR16( devAddr, EC_SB_REG_CSI_OFS1__A ,0x0001 , 0x0000);
WR16( devAddr, EC_SB_REG_CSI_OFS2__A ,0x0001 , 0x0000);
WR16( devAddr, EC_SB_REG_CSI_LO__A ,0x000c , 0x0000);
WR16( devAddr, EC_SB_REG_CSI_HI__A ,0x0018 , 0x0000);
WR16( devAddr, EC_SB_REG_SNR_HI__A ,0x007f , 0x0000);
WR16( devAddr, EC_SB_REG_SNR_MID__A ,0x007f , 0x0000);
WR16( devAddr, EC_SB_REG_SNR_LO__A ,0x007f , 0x0000);
WR16( devAddr, EC_OC_REG_DTO_CLKMODE__A ,0x0002 , 0x0000);
WR16( devAddr, EC_OC_REG_DTO_PER__A ,0x0006 , 0x0000);
WR16( devAddr, EC_OC_REG_DTO_BUR__A ,0x0001 , 0x0000);
WR16( devAddr, EC_OC_REG_RCR_CLKMODE__A ,0x0000 , 0x0000);
WR16( devAddr, EC_OC_REG_RCN_GAI_LVL__A ,0x000D , 0x0000);
WR16( devAddr, EC_OC_REG_OC_MPG_SIO__A ,0x0000 , 0x0000);
/* Needed because shadow registers do not have correct default value */
WR16( devAddr, EC_OC_REG_RCN_CST_LOP__A ,0x1000 , 0x0000);
WR16( devAddr, EC_OC_REG_RCN_CST_HIP__A ,0x0000 , 0x0000);
WR16( devAddr, EC_OC_REG_RCN_CRA_LOP__A ,0x0000 , 0x0000);
WR16( devAddr, EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 , 0x0000);
WR16( devAddr, EC_OC_REG_RCN_CLP_LOP__A ,0x0000 , 0x0000);
WR16( devAddr, EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 , 0x0000);
WR16( devAddr, EC_OC_REG_DTO_INC_LOP__A ,0x0000 , 0x0000);
WR16( devAddr, EC_OC_REG_DTO_INC_HIP__A ,0x00C0 , 0x0000);
WR16( devAddr, EC_OD_REG_SYNC__A ,0x0664 , 0x0000);
WR16( devAddr, EC_RS_REG_REQ_PCK_CNT__A ,0x1000 , 0x0000);
WR16( devAddr, EC_COMM_EXEC__A ,0x0001 , 0x0000);
#endif /* DRXD_TYPE_B */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
/**
* \fn DRXStatus_t ResetEC( const pDRXDemodInstance_t demod )
* \brief
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
#if DRXD_TYPE_A
static DRXStatus_t
ResetEC( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
pDRX3973DData_t extAttr=NULL;
static u8_t resetData3[] =
{ 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
0x03,0x00 /* EC_OC_REG_TMD_CUR_CNT__A */
};
static u8_t resetData4[] =
{ 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
0x02,0x00 /* EC_OC_REG_AVR_BSH_CNT__A */
};
static u8_t resetData5[] =
{ 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */
0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */
0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */
0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */
0x0A,0x00 /* EC_OC_REG_RCN_GAI_LVL__A */
};
static u8_t resetData6[] =
{ 0xFF,0xFF, /* EC_OC_REG_RCN_CLP_LOP__A */
0xFF,0x00 /* EC_OC_REG_RCN_CLP_HIP__A */
};
devAddr = demod -> myI2CDevAddr;
extAttr = (pDRX3973DData_t) demod -> myExtAttr;
WR16( devAddr, EC_OC_REG_COMM_EXEC__A , 0x0000, 0x0000);
WR16( devAddr, EC_OD_REG_COMM_EXEC__A , 0x0000, 0x0000);
WRBLOCK( devAddr, EC_OC_REG_TMD_TOP_MODE__A , sizeof(resetData3), resetData3 );
WRBLOCK( devAddr, EC_OC_REG_AVR_ASH_CNT__A , sizeof(resetData4), resetData4 );
WRBLOCK( devAddr, EC_OC_REG_RCN_MODE__A , sizeof(resetData5), resetData5 );
WRBLOCK( devAddr, EC_OC_REG_RCN_CLP_LOP__A , sizeof(resetData6), resetData6 );
WR16( devAddr, EC_OD_REG_SYNC__A , 0x0664 , 0x0000);
WR16( devAddr, EC_OC_REG_OC_MON_SIO__A , 0x0000, 0x0000);
WR16( devAddr, EC_OC_REG_SNC_ISC_LVL__A , 0x0422, 0x0000);
if ( (extAttr->consumerDevice) == TRUE )
{
/* Output zero on monitorbus pads, power saving */
WR16( devAddr, EC_OC_REG_OCR_MON_UOS__A ,
( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ), 0x0000);
WR16( devAddr, EC_OC_REG_OCR_MON_WRI__A,
EC_OC_REG_OCR_MON_WRI_INIT, 0x0000);
}
WR16( devAddr, EC_OD_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, EC_OC_REG_COMM_EXEC__A , 0x0001, 0x0000);
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
#endif /* DRXD_TYPE_A */
/*============================================================================*/
/**
* \fn DRXStatus_t InitSC( const pDRXDemodInstance_t demod )
* \brief
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitSC( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
devAddr = demod -> myI2CDevAddr;
/*=================================*/
/* Reset SC */
/*=================================*/
WR16( devAddr, SC_CT_REG_COMM_EXEC__A, 0 ,0x0000);
WR16( devAddr, SC_CT_REG_COMM_STATE__A, 0 ,0x0000);
#ifdef COMPILE_FOR_QT
WR16( devAddr, SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ,0x0000);
#endif
/* SC is not started, this is done in SetChannels() */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
#ifdef USE_LC_INIT
/**
* \fn DRXStatus_t InitLC( const pDRXDemodInstance_t demod )
* \brief
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitLC( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
/* DRXD_TYPE_A & DRXD_TYPE_B settings */
static u8_t resetData1[] =
{ 0xE6,0xFF, /* LC_RA_RAM_PROC_DELAY_IF__A */
0xE3,0xFF, /* LC_RA_RAM_PROC_DELAY_FS__A */
#ifdef COMPILE_FOR_QT
/* LC version 0.1.32 */
0x00,0x01, /* LC_RA_RAM_LOCK_TH_CRMM__A */
0x00,0x05 /* LC_RA_RAM_LOCK_TH_SRMM__A */
#else
/* LC version 0.1.67 and higher */
0x64,0x00, /* LC_RA_RAM_LOCK_TH_CRMM__A */
0x64,0x00 /* LC_RA_RAM_LOCK_TH_SRMM__A */
#endif
};
static u8_t resetData2[] =
{ 0x0F,0x00, /* LC_RA_RAM_MODE_FILTER__A */
0x00,0x40, /* LC_RA_RAM_WEIGHT_CP_CRMM__A */
0x00,0x40, /* LC_RA_RAM_WEIGHT_CE_CRMM__A */
0x00,0x04, /* LC_RA_RAM_GAIN_PHASE__A */
0x00,0x04, /* LC_RA_RAM_GAIN_DELAY__A */
0xFF,0x7F, /* LC_RA_RAM_THRESHOLD_CRMM__A */
0xFF,0x7F, /* LC_RA_RAM_THRESHOLD_SRMM__A */
0x00,0x00, /* LC_RA_RAM_OFFSET_ADJUST_CRMM__A */
0x00,0x00, /* LC_RA_RAM_OFFSET_ADJUST_SRMM__A */
0x00,0x00, /* LC_R⌨️ 快捷键说明
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