📄 drx3973d.c
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}
else
{
/* 4-20 MHz pad, PLL bypassed */
WR16( devAddr, CC_REG_PLL_MODE__A, 0x2 , 0);
}
/* when power down , clock & PLL down, osc up */
/* trigger CC to take over the new settings */
WR16( devAddr, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY , 0);
#endif
return (DRX_STS_OK);
#ifndef COMPILE_FOR_QT
rw_error:
return (DRX_STS_ERROR);
#endif
}
/*============================================================================*/
/**
* \fn DRXStatus_t InitFE( const pDRXDemodInstance_t demod )
* \brief
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitFE( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
pDRX3973DData_t extAttr=NULL;
#if (DRXD_TYPE_A)
static u8_t resetData1[] =
{ 0x00,0x00, /* FE_AD_REG_PD__A */
0x01,0x00, /* FE_AD_REG_INVEXT__A */
0x00,0x00 /* FE_AD_REG_CLKNEG__A */
};
static u8_t resetData2[] =
{ 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
0x10,0x00 /* FE_AG_REG_DCE_RUR_CNT__A */
};
static u8_t resetData3[] =
{ 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
0x00,0x00 /* FE_AG_REG_ACE_RUR_CNT__A */
};
static u8_t resetData4[] =
{ 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */
0x00,0x00 /* FE_AG_REG_EGC_FLA_DEC__A */
};
static u8_t resetData5[] =
{ 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
0x00,0xFE /* FE_AG_REG_GC1_AGC_MIN__A */
};
static u8_t resetData6[] =
{ 0x00,0x00, /* FE_AG_REG_IND_WIN__A */
0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */
0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */
0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */
0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */
0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */
0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
0x02,0x00, /* FE_AG_REG_PDC_MAX__A */
0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */
0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */
0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */
0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
};
static u8_t resetData7[] =
{ 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
0x00,0x00 /* FE_AG_REG_BGC_CGC_WRI__A */
};
static u8_t resetData8[] =
{ 0x05,0x00, /* FE_FD_REG_SCL__A */
0x03,0x00, /* FE_FD_REG_MAX_LEV__A */
0x05,0x00 /* FE_FD_REG_NR__A */
};
static u8_t resetData9[] =
{ 0x16,0x00, /* FE_CF_REG_SCL__A */
0x04,0x00, /* FE_CF_REG_MAX_LEV__A */
0x06,0x00, /* FE_CF_REG_NR__A */
0x00,0x00, /* FE_CF_REG_IMP_VAL__A */
0x01,0x00 /* FE_CF_REG_MEAS_VAL__A */
};
static u8_t resetData10[] =
{ 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */
0x00,0x00 /* FE_CU_REG_FRM_CNT_STR__A */
};
devAddr = demod -> myI2CDevAddr;
extAttr = (pDRX3973DData_t) demod -> myExtAttr;
WRBLOCK( devAddr, FE_AD_REG_PD__A , sizeof(resetData1), resetData1 );
WRBLOCK( devAddr, FE_AG_REG_DCE_AUR_CNT__A , sizeof(resetData2), resetData2 );
WRBLOCK( devAddr, FE_AG_REG_ACE_AUR_CNT__A , sizeof(resetData3), resetData3 );
WRBLOCK( devAddr, FE_AG_REG_EGC_FLA_RGN__A , sizeof(resetData4), resetData4 );
WRBLOCK( devAddr, FE_AG_REG_GC1_AGC_MAX__A , sizeof(resetData5), resetData5 );
WRBLOCK( devAddr, FE_AG_REG_IND_WIN__A , sizeof(resetData6), resetData6 );
WRBLOCK( devAddr, FE_AG_REG_BGC_FGC_WRI__A , sizeof(resetData7), resetData7 );
WRBLOCK( devAddr, FE_FD_REG_SCL__A , sizeof(resetData8), resetData8 );
WRBLOCK( devAddr, FE_CF_REG_SCL__A , sizeof(resetData9), resetData9 );
WRBLOCK( devAddr, FE_CU_REG_FRM_CNT_RST__A , sizeof(resetData10), resetData10 );
/* with or without PGA */
if ( ( demod->myDemodFunct->typeId == DRX3973D_TYPE_ID ) ||
( demod->myDemodFunct->typeId == DRX3974D_TYPE_ID ) ||
( demod->myDemodFunct->typeId == DRX3977D_TYPE_ID ) )
{
/* with PGA */
WR16( devAddr, FE_AG_REG_AG_PGA_MODE__A , 0x0004, 0x0000);
} else {
/* withou PGA */
WR16( devAddr, FE_AG_REG_AG_PGA_MODE__A , 0x0001, 0x0000);
}
WR16( devAddr, FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );
WR16( devAddr, FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );
WR16( devAddr, FE_AG_REG_CDR_RUR_CNT__A, 0x0010, 0x0000 );
WR16( devAddr, FE_AG_REG_FGM_WRI__A , 48, 0x0000 );
/* Activate measurement, activate scale */
WR16( devAddr, FE_FD_REG_MEAS_VAL__A , 0x0001, 0x0000 );
WR16( devAddr, FE_CU_REG_COMM_EXEC__A, 0x0001, 0x0000 );
WR16( devAddr, FE_CF_REG_COMM_EXEC__A, 0x0001, 0x0000 );
WR16( devAddr, FE_IF_REG_COMM_EXEC__A, 0x0001, 0x0000 );
WR16( devAddr, FE_FD_REG_COMM_EXEC__A, 0x0001, 0x0000 );
WR16( devAddr, FE_FS_REG_COMM_EXEC__A, 0x0001, 0x0000 );
WR16( devAddr, FE_AD_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, FE_AG_REG_COMM_EXEC__A , 0x0001, 0x0000);
WR16( devAddr, FE_AG_REG_AG_MODE_LOP__A , 0x895E, 0x0000);
#endif /* DRXD_TYPE_A */
#if (DRXD_TYPE_B)
devAddr = demod -> myI2CDevAddr;
extAttr = (pDRX3973DData_t) demod -> myExtAttr;
WR16( devAddr, FE_AD_REG_PD__A ,0x0000 , 0x0000 );
WR16( devAddr, FE_AD_REG_CLKNEG__A ,0x0000 , 0x0000 );
WR16( devAddr, FE_AG_REG_AG_PWD__A ,0x0000 , 0x0000 );
WR16( devAddr, FE_AG_REG_BGC_FGC_WRI__A ,0x0000 , 0x0000 );
WR16( devAddr, FE_AG_REG_BGC_CGC_WRI__A ,0x0000 , 0x0000 );
WR16( devAddr, FE_AG_REG_AG_MODE_LOP__A ,0x000a , 0x0000 );
WR16( devAddr, FE_AG_REG_IND_PD1_WRI__A ,35 , 0x0000 );
WR16( devAddr, FE_AG_REG_IND_WIN__A ,0 , 0x0000 );
WR16( devAddr, FE_AG_REG_IND_THD_LOL__A ,8 , 0x0000 );
WR16( devAddr, FE_AG_REG_IND_THD_HIL__A ,8 , 0x0000 );
WR16( devAddr, FE_CF_REG_IMP_VAL__A ,1 , 0x0000 );
WR16( devAddr, FE_AG_REG_EGC_FLA_RGN__A ,7 , 0x0000 );
/* with or without PGA */
if ( ( demod->myDemodFunct->typeId == DRX3973D_TYPE_ID ) ||
( demod->myDemodFunct->typeId == DRX3974D_TYPE_ID ) ||
( demod->myDemodFunct->typeId == DRX3977D_TYPE_ID ) )
{
/* with PGA */
WR16( devAddr, FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000);
} else {
/* withou PGA */
WR16( devAddr, FE_AG_REG_AG_PGA_MODE__A , 0x0001, 0x0000);
}
WR16( devAddr, FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );/*added HS 23-05-2005*/
WR16( devAddr, FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );
WR16( devAddr, FE_COMM_EXEC__A ,0x0001 , 0x0000 );
/* RF-AGC setup */
WR16( devAddr, FE_AG_REG_PDA_AUR_CNT__A , 0x0C, 0x0000 );
WR16( devAddr, FE_AG_REG_PDC_SET_LVL__A , 0x01, 0x0000 );
WR16( devAddr, FE_AG_REG_PDC_FLA_RGN__A , 0x02, 0x0000 );
WR16( devAddr, FE_AG_REG_PDC_FLA_STP__A , 0xFFFF, 0x0000 );
WR16( devAddr, FE_AG_REG_PDC_SLO_STP__A , 0xFFFF, 0x0000 );
WR16( devAddr, FE_AG_REG_PDC_MAX__A , 0x02, 0x0000 );
WR16( devAddr, FE_AG_REG_TGA_AUR_CNT__A , 0x0C, 0x0000 );
WR16( devAddr, FE_AG_REG_TGC_SET_LVL__A , 0x22, 0x0000 );
WR16( devAddr, FE_AG_REG_TGC_FLA_RGN__A , 0x15, 0x0000 );
WR16( devAddr, FE_AG_REG_TGC_FLA_STP__A , 0x01, 0x0000 );
WR16( devAddr, FE_AG_REG_TGC_SLO_STP__A , 0x0A, 0x0000 );
#endif /* DRXD_TYPE_B */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
/**
* \fn DRXStatus_t InitFT( const pDRXDemodInstance_t demod )
* \brief Initilize FT
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitFT( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
devAddr = demod -> myI2CDevAddr;
WR16( devAddr, FT_REG_COMM_EXEC__A, 0x0001, 0x0000 );
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
/**
* \fn DRXStatus_t InitCP( const pDRXDemodInstance_t demod )
* \brief Initialize CP
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitCP( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
#if (DRXD_TYPE_A)
static u8_t resetData1[] =
{ 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */
0x0A,0x00 /* CP_REG_BR_STR_DEL__A */
};
static u8_t resetData2[] =
{ 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */
0x00,0x00, /* CP_REG_RT_ANG_INC1__A */
0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */
0x03,0x00 /* CP_REG_RT_DETECT_TRH__A */
};
static u8_t resetData3[] =
{ 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */
0x62,0x00, /* CP_REG_AC_AVER_POW__A */
0x82,0x00, /* CP_REG_AC_MAX_POW__A */
0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */
0x0F,0x00 /* CP_REG_AC_WEIGHT_EXP__A */
};
static u8_t resetData4[] =
{ 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */
0x01,0x00 /* CP_REG_AC_AMP_FIX__A */
};
devAddr = demod -> myI2CDevAddr;
WRBLOCK( devAddr, CP_REG_BR_SPL_OFFSET__A , sizeof(resetData1), resetData1 );
WRBLOCK( devAddr, CP_REG_RT_ANG_INC0__A , sizeof(resetData2), resetData2 );
WRBLOCK( devAddr, CP_REG_AC_NEXP_OFFS__A , sizeof(resetData3), resetData3 );
WRBLOCK( devAddr, CP_REG_AC_AMP_MODE__A , sizeof(resetData4), resetData4 );
WR16( devAddr, CP_REG_INTERVAL__A , 0x0005, 0x0000);
WR16( devAddr, CP_REG_RT_EXP_MARG__A , 0x0004, 0x0000);
WR16( devAddr, CP_REG_AC_ANG_MODE__A , 0x0003, 0x0000);
WR16( devAddr, CP_REG_COMM_EXEC__A , 0x0001, 0x0000);
#endif /* DRXD_TYPE_A */
#if (DRXD_TYPE_B)
devAddr = demod -> myI2CDevAddr;
WR16( devAddr, CP_REG_BR_SPL_OFFSET__A ,0x0008 ,0x0000);
WR16( devAddr, CP_COMM_EXEC__A ,0x0001 ,0x0000);
#endif /* DRXD_TYPE_B */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
}
/*============================================================================*/
/**
* \fn DRXStatus_t InitCE( const pDRXDemodInstance_t demod )
* \brief Inmitialize CE.
* \param demod pointer to demod data.
* \return DRXStatus_t Return status.
*\retval DRX_STS_OK Success.
*\retval DRX_STS_ERROR Failure.
*/
static DRXStatus_t
InitCE( const pDRXDemodInstance_t demod )
{
pI2CDeviceAddr_t devAddr=NULL;
#if (DRXD_TYPE_A)
static u8_t resetData1[] =
{ 0x62,0x00, /* CE_REG_AVG_POW__A */
0x78,0x00, /* CE_REG_MAX_POW__A */
0x62,0x00, /* CE_REG_ATT__A */
0x17,0x00 /* CE_REG_NRED__A */
};
static u8_t resetData2[] =
{ 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */
0xEB,0xFF /* CE_REG_NE_TD_CAL__A */
};
static u8_t resetData3[] =
{ 0x06,0x00, /* CE_REG_NE_MIXAVG__A */
0x00,0x00 /* CE_REG_NE_NUPD_OFS__A */
};
static u8_t resetData4[] =
{ 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */
0x00,0x00 /* CE_REG_PE_TIMESHIFT__A */
};
static u8_t resetData5[] =
{ 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */
0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
0x0E,0x00 /* CE_REG_TP_A0_MU_LMS_STEP__A */
};
static u8_t resetData6[] =
{ 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */
0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
0x0A,0x00 /* CE_REG_TP_A1_MU_LMS_STEP__A */
};
static u8_t resetData7[] =
{ 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */
0x0C,0x00 /* CE_REG_FI_EXP_NORM__A */
};
static u8_t resetData8[] =
{ 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */
0x00,0x00, /* CE_REG_IR_STARTPOS__A */
0xFF,0x00 /* CE_REG_IR_NEXP_THRES__A */
};
devAddr = demod -> myI2CDevAddr;
WRBLOCK( devAddr, CE_REG_AVG_POW__A , sizeof(resetData1), resetData1 );
WRBLOCK( devAddr, CE_REG_NE_ERR_SELECT__A , sizeof(resetData2), resetData2 );
WRBLOCK( devAddr, CE_REG_NE_MIXAVG__A , sizeof(resetData3), resetData3 );
WRBLOCK( devAddr, CE_REG_PE_NEXP_OFFS__A , sizeof(resetData4), resetData4 );
WRBLOCK( devAddr, CE_REG_TP_A0_TAP_NEW__A , sizeof(resetData5), resetData5 );
WRBLOCK( devAddr, CE_REG_TP_A1_TAP_NEW__A , sizeof(resetData6), resetData6 );
WRBLOCK( devAddr, CE_REG_FI_SHT_INCR__A , sizeof(resetData7), resetData7 );
WRBLOCK( devAddr, CE_REG_IR_INPUTSEL__A , sizeof(resetData8), resetData8 );
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