dm9000end.c

S3C2410的DM9000驱动。在优龙的开发板子上调试成功

/* dm9000End.c - dm9000 END  network interface driver */
/* Copyright Reserevd all by Davicom Semiconductor CO.,LTD */
/* version 1.0     				           */
#include "copyright_wrs.h"

#include "vxWorks.h"
#include "endLib.h"			/* Common END structures. */
#include "end.h"
#include "etherLib.h"
#include "etherMultiLib.h"
#include "netLib.h"
#include "cacheLib.h"
#include "lstLib.h"			/* Needed to maintain protocol list. */
#include "iv.h"
#include "stdlib.h"
#include "sysLib.h"
#include "intLib.h"
#include "taskLib.h"
#include "lpc2210.h"
#include "wrSbcArm7.h"
#define	INT_NUM_IRQ0		0xe0	/* vector number for IRQ0 */
     



IMPORT  int endMultiLstCnt (END_OBJ* pEnd);
/*#define printf      SysDebugPrint*/

#define	NET_RST0			0x00000100
#define	BUS_DELAY			10

#define EEmyMAC             0x00
#define EEmyIP              0x30
#define EEhostIP            0x34

/* defines */
#define UCHAR               unsigned char
#define UWORD               unsigned short int

#define DM9000_REG00        0x00
#define DM9000_REG05        0x30    /* SKIP_CRC/SKIP_LONG whz modify*/ 
#define DM9000_REG08        0x27   /*old =0x3f */
#define DM9000_REG09        0x38
#define DM9000_REG0A        0x08
#define DM9000_REGFF        0x83    /*0x8F     IMR */

#define DM9000_PHY          0x40    /* PHY address 0x01 */
#define DM9000_PKT_MAX      1536    /* Received packet max size */
#define DM9000_PKT_RDY      0x01    /* Packet ready to receive */
#define DM9000_MIN_IO       0x300
#define DM9000_MAX_IO       0x370
#define DM9000_INT_MII      0x00
#define DM9000_EXT_MII      0x80

#define DM9000_10MHD        0
#define DM9000_100MHD       1
#define DM9000_10MFD        4
#define DM9000_100MFD       5
#define DM9000_AUTO         8
#define DM9000_1M_HPNA      0x10

#define DM9000_MEDIA_MODE   DM9000_AUTO

#define FASTETHER_NIC       0
#define HOMERUN_NIC         1
#define LONGRUN_NIC         2

#define DM9801_NOISE_FLOOR  0x08
#define DM9802_NOISE_FLOOR  0x05

#define DM9000_DEV_NAME     "dm"
#define DM9000_DEV_NAME_LEN 3

/* Configuration items */

#define END_BUFSIZ      (ETHERMTU + ENET_HDR_REAL_SIZ + 6)
#define EH_SIZE         (14)
#define END_SPEED_10M   10000000    /* 10Mbs */
#define END_SPEED_100M  100000000   /* 100Mbs */
#define END_SPEED       END_SPEED_10M


#undef htons
#define htons(x)  ((((x)&0xff00)>>8)|((x)&0x00ff)<<8)

/* Cache macros */

#define END_CACHE_INVALIDATE(address, len) \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))

#define END_CACHE_PHYS_TO_VIRT(address) \
        CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->cacheFuncs, (address))

#define END_CACHE_VIRT_TO_PHYS(address) \
        CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->cacheFuncs, (address))

/*
 * Default macro definitions for BSP interface.
 * These macros can be redefined in a wrapper file, to generate
 * a new module with an optimized interface.
 */

/* Macro to connect interrupt handler to vector */

#ifndef SYS_INT_CONNECT
#define SYS_INT_CONNECT(pDrvCtrl,rtn,arg,pResult) \
	{ \
    IMPORT STATUS sysIntConnect();  \
	*pResult = intConnect (pDrvCtrl->ivec, \
			     rtn, (int)arg); \
	}
#endif

/* Macro to disconnect interrupt handler from vector */

#ifndef SYS_INT_DISCONNECT
#define SYS_INT_DISCONNECT(pDrvCtrl,rtn,pResult) \
	{ \
   *pResult = OK; /* HELP: need a real routine */ \
   }
#endif

/* Macro to enable the appropriate interrupt level */

#ifndef SYS_INT_ENABLE
#define SYS_INT_ENABLE(pDrvCtrl) \
	{ \
	IMPORT STATUS intEnable(); \
	intEnable (pDrvCtrl->ilevel); \
	}
#endif

#ifndef	SYS_INT_DISABLE
#define	SYS_INT_DISABLE(pDrvCtrl) \
	{ \
	IMPORT STATUS intDisable(); \
	intDisable (pDrvCtrl->ilevel); \
	}
#endif

/* Macro to get the ethernet address from the BSP */


/*
 * Macros to do a short (UINT16) access to the chip. Default
 * assumes a normal memory mapped device.
 */
#define DM9000_IOADDR       0x83000000
#define DM9000_IODATA       0x83000004

#ifndef DM9000_OUT_CHAR
#define DM9000_OUT_CHAR(addr,value)\
    dm9000OutChar(addr,value);
#endif
/*void DM9000_OUT_CHAR(unsidned long addr,UCHAR value)
{
	sysOutByte( DM9000_IOADDR,addr);
    sysOutByte( DM9000_IODATA,value);
}*/
#ifndef DM9000_IN_CHAR
#define DM9000_IN_CHAR(addr,data)\
	data = dm9000InChar(addr);
#endif

#ifndef DM9000_IN_ADDR
#define DM9000_IN_ADDR( addr ) \
    addr = sysInByte( (DM9000_IOADDR));
#endif

#ifndef DM9000_OUT_ADDR
#define DM9000_OUT_ADDR( addr ) \
    sysOutByte(DM9000_IOADDR,addr);
#endif

#ifndef DM9000_IN_BYTE
#define DM9000_IN_BYTE( data ) \
    data=sysInByte( (DM9000_IODATA));
#endif

#ifndef DM9000_OUT_BYTE
#define DM9000_OUT_BYTE( data ) \
    sysOutByte( (DM9000_IODATA),(data));
#endif

#ifndef DM9000_IN_WORD
#define DM9000_IN_WORD( data ) \
        data = sysInWord( DM9000_IODATA);
#endif
    
#ifndef DM9000_OUT_WORD
#define DM9000_OUT_WORD( data ) \
        sysOutWord( (DM9000_IODATA),data);
#endif

/* A shortcut for getting the hardware address from the MIB II stuff. */

#define END_HADDR(pEnd) \
        ((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)

#define END_HADDR_LEN(pEnd) \
        ((pEnd)->mib2Tbl.ifPhysAddress.addrLength)

/* typedefs */

typedef struct
{
    int len;
    char * pData;
} PKT;  /* A dummy DMA data packet */

#define DM9000_PKT_LEN_GET(pPkt) (((PKT *)pPkt)->len)
#define DM9000_PKT_DATA_GET(pPkt) (((PKT *)pPkt)->pData)

typedef struct rfd
{
    PKT *  pPkt;
    struct rfd * next;
} RFD;  /* dummy rx frame descriptor */

/* The definition of the driver control structure */

typedef struct end_device
{
    END_OBJ             end;            /* The class we inherit from. */
    END_ERR             err;
    int                 unit;           /* unit number */
    int                 ivec;           /* interrupt vector */
    int                 ilevel;         /* interrupt level */
    long                flags;          /* Our local flags. */
    UCHAR               enetAddr[6];    /* ethernet address */

    CACHE_FUNCS         cacheFuncs;     /* cache function pointers */
    CL_POOL_ID          pClPoolId;      /* cluster pool */
    BOOL                rxHandling;     /* rcv task is scheduled */

    UCHAR               io_mode;        /* 0:word, 2:byte */
    char                tx_pkt_cnt;
    char                device_wait_reset;
    UWORD               queue_pkt_len;
    UCHAR               reg0;           /* registers saved */
    UCHAR               nic_type;       /* NIC type */
    UCHAR               op_mode;        /* PHY operation mode */

    UCHAR               mcastFilter[8]; /* multicast filter */
    int                 txBuf[ETHERMTU + EH_SIZE + 6 + 64];

	int					tbusy;
} END_DEVICE;

/*
 * This will only work if there is only a single unit, for multiple
 * unit device drivers these should be integrated into the END_DEVICE
 * structure.
 */

M_CL_CONFIG dm9000MclBlkConfig =    /* network mbuf configuration table */
{
    /*
    no. mBlks       no. clBlks  memArea     memSize
    -----------     ----------  -------     -------
    */
    0,          0,      NULL,       0
};

CL_DESC dm9000ClDescTbl [] =    /* network cluster pool configuration table */
{
    /*
    clusterSize         num memArea     memSize
    -----------         ----    -------     -------
    */
    {END_BUFSIZ,    0,  NULL,       0}
};

int dm9000ClDescTblNumEnt = (NELEMENTS(dm9000ClDescTbl));

NET_POOL dm9000CmpNetPool;

/* Definitions for the flags field */

#define DM9000_PROMISCUOUS  0x1
#define DM9000_POLLING      0x2

/* Status register bits, returned by dm9000StatusRead() */

#define DM9000_RINT         0x1     /* Rx interrupt pending */
#define DM9000_TINT         0x2     /* Tx interrupt pending */
#define DM9000_VALID_INT    0x3     /* Any valid interrupt pending */
#define DM9000_RXON         0x4     /* Rx on (enabled) */
#define DM9000_TFULL        0x8     /* tx full */
#define DM9000_RXRDY        0x10    /* data rdy */

#define DM9000_MIN_FBUF     (1536)  /* min first buffer size */

/* DEBUG MACROS */

#ifdef DEBUG
#endif /* ENDDEBUG */

#undef DRV_DEBUG
#define DRV_DEBUG 
#define  INT_LOCK()	

#define  INT_UNLOCK(x)	


 int    g_RecvNumError=0;
int	g_RecvNum=0;
int     g_IntrNum=0;
#ifdef  DRV_DEBUG
#define DRV_DEBUG_OFF           0x0000
#define DRV_DEBUG_NO            0x0000
#define DRV_DEBUG_RX            0x0001
#define DRV_DEBUG_TX            0x0002
#define DRV_DEBUG_INT           0x0004
#define DRV_DEBUG_POLL          0x0008
#define DRV_DEBUG_POLL_RX       0x0010
#define DRV_DEBUG_POLL_TX       0x0020
#define DRV_DEBUG_LOAD          0x0040
#define DRV_DEBUG_IOCTL         0x0080
#define DRV_DEBUG_IO            0x0100
#define DRV_DEBUG_STATUS        0x0200
#define DRV_DEBUG_POLL_REDIR    0x0400
#define DRV_DEBUG_LOG_NVRAM     0x0800
#define DRV_PK                  0x1000

int     dm9000Debug = 1;
int     dm9000TxInts = 0;
static  char dbg_array[]={0x0d,0x0a,'\0'};
extern void whz_puts( char * );
extern void whz_puthex( unsigned long int );
#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)			\
    {									\
    if (dm9000Debug & FLG)						\
	if (_func_logMsg != NULL)					\
	    _func_logMsg (X0, X1, X2, X3, X4, X5, X6);			\
}

#define DRV_SP( FLG, X0 )\
    {\
    if( dm9000Debug & FLG )\
    {\
        printf(X0);\
    }\
    }

#else /*DRV_DEBUG*/
#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
#define DRV_SP( FLG, X0 )
#endif /*DRV_DEBUG*/

/* LOCALS */
static UCHAR  nfloor = 0;
unsigned long CrcTable[256] = {
   0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL,
   0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L,
   0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L,
   0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L,
   0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL,
   0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L,
   0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL,
   0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L,
   0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L,
   0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL,
   0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L,
   0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L,
   0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L,
   0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL,
   0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L,
   0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL,
   0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL,
   0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L,
   0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L,
   0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L,
   0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL,
   0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L,
   0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL,
   0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L,
   0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L,
   0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL,
   0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L,
   0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L,
   0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L,
   0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL,
   0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L,
   0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL,
   0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL,
   0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L,
   0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L,
   0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L,
   0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL,
   0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L,
   0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL,
   0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L,
   0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L,
   0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL,
   0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L,
   0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L,
   0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L,
   0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL,
   0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L,
   0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL,
   0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL,
   0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L,
   0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L,
   0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L,
   0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL,
   0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L,
   0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL,
   0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L,
   0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L,
   0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL,
   0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L,
   0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L,
   0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L,
   0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL,
   0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L,
   0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL
};


/* forward static functions */
static void     dmfe_reset_dm9000( END_DEVICE *dev );
static void     dmfe_config_dm9000( END_DEVICE *dev, int oo);
static int      dmfe_start_xmit( PKT *skb, END_DEVICE *dev);
static int      dmfe_packet_receive( PKT *skb, END_DEVICE *dev );
static int      dmfe_stop_dm9000(END_DEVICE *dev);
static void     identify_nic( END_DEVICE *dev );
static void     set_PHY_mode( END_DEVICE *dev );