📄 wrsbcarm7.h
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/* sbcarm7.h - WindRiver SBC ARM7 header file */
/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01o,28jul04,a_m BSP定制 for 精英arm7开发板
01f,16jul02,m_h C++ protection
01e,04jan02,m_h minor cleanup
01d,03dec01,m_h remove Diab warnings
01c,27sep01,m_h base MAC address on user DIP setting
01b,22may01,m_h documentation
01a,12apr01,m_h created from snds100 template.
*/
/*
This file contains I/O address and related constants for the SBC ARM7 board.
*/
#ifndef INCsbcarm7h
#define INCsbcarm7h
#ifdef __cplusplus
extern "C" {
#endif
#include "lpc2210.h"
#define TARGET_SBCARM7
#define SBCARM7_FLASH_BASE 0x1000000
/*
* Local-to-Bus memory address constants:
* the local memory address always appears at 0 locally;
* it is not dual ported.
*/
/* : 0x00000000->0x0c000000 */
#define LOCAL_MEM_LOCAL_ADRS 0x81000000 /* fixed */
#define LOCAL_MEM_BUS_ADRS 0x00000000 /* fixed */
#define BUS BUS_TYPE_NONE
/* definitions for the KS32C50100 UART */
#define N_SBCARM7_UART_CHANNELS 1 /* number of SBCARM7 UART chans */
#define N_SIO_CHANNELS N_SBCARM7_UART_CHANNELS
#define N_UART_CHANNELS N_SBCARM7_UART_CHANNELS
/* LED Registers (write) */
#define SBCARM7_LEDREG 0x3fd4000
/* USER DIP switch (read) */
#define SBCARM7_USERREG 0x3fd4000
#define READ_USERDIP() (*((volatile char *)SBCARM7_USERREG) & 0xff)
/*************************************************************************
*
* DRAM Memory Bank 0 area MAP for Exception vector table
* and Stack, User code area.
*
*/
/* : 0x00000000->0x0c000000 */
#define DRAM_BASE 0x80200000 /* Final start address of DRAM */
#define DRAM_LIMIT 0x200000
/* : 0x1000000->0x0c000000 */
#define RESET_DRAM_START 0x80200000 /* Start of DRAM on power-up */
#define RESET_ROM_START 0x80000000 /* Start of ROM on power-up */
/****************************************************************************
*
* Format of the Program Status Register
*/
#define FBit 0x40
#define IBit 0x80
#define LOCKOUT 0xC0 /* Interrupt lockout value */
#define LOCK_MSK 0xC0 /* Interrupt lockout mask value */
#define MODE_MASK 0x1F /* Processor Mode Mask */
#define UDF_MODE 0x1B /* Undefine Mode(UDF) */
#define ABT_MODE 0x17 /* Abort Mode(ABT) */
#define SUP_MODE 0x13 /* Supervisor Mode (SVC) */
#define IRQ_MODE 0x12 /* Interrupt Mode (IRQ) */
#define FIQ_MODE 0x11 /* Fast Interrupt Mode (FIQ) */
#define USR_MODE 0x10 /* User Mode(USR) */
/*************************************************************************
* SYSTEM CLOCK
*/
#define MHz 1000000
/* : 50->66 */
#define fMCLK_MHz 60000000 /* 50MHz, KS32C50100*/
#define fMCLK 60 /* fMCLK_MHz/MHz */
/*************************************************************************
* SYSTEM MEMORY CONTROL REGISTER EQU TABLES
*/
/* SYSCFG Register Value */
/* : deleted */
/*#define SYSCONFIG_VAL 0x07ffffa0*/ /* System Configuration Value, EDO RAM */
/* : 0x87ffffa0->0x00000000 */
#define SYSCONFIG_VAL_SDRAM 0x0000000e /* System Configuration Value, SDRAM */
/* CLKCON Clock configuration register Values */
#define tCDIV (0<<0)
#define tWE (0<<16)
#define tMUX (0<<17)
#define tAC (0<<18)
#define tTEST (0<<31)
/*#define rCLKCON (tCDIV+tWE+tMUX+tAC+tTEST)*/
/* : deleted and added */
#define rCLKCON 0x7ff8 /*All unit block CLK enable*/
/* EXTACONx External I/O access timing register Values */
#define tCOS0 (1<<0)
#define tACS0 (1<<3)
#define tCOH0 (1<<6)
#define tACC0 (1<<9)
#define tCOS1 (1<<16)
#define tACS1 (1<<19)
#define tCOH1 (1<<22)
#define tACC1 (1<<25)
#define rEXTACON0 (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)
#define tCOS2 (7<<0)
#define tACS2 (7<<3)
#define tCOH2 (7<<6)
#define tACC2 (7<<9)
#define tCOS3 (7<<16)
#define tACS3 (7<<19)
#define tCOH3 (7<<22)
#define tACC3 (7<<25)
#define rEXTACON1 (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)
/***********************************************************
*
* -> EXTDBWTH : Memory Bus Width register
*/
#define DSR0 (3<<0) /* ROM0, 0 : Disable, 1 : Byte etc.*/
#define DSR1 (1<<2) /* ROM1 */
#define DSR2 (1<<4) /* ROM2 */
#define DSR3 (0<<6) /* ROM3 */
#define DSR4 (0<<8) /* ROM4 */
#define DSR5 (0<<10) /* ROM5 */
#define DSD0 (3<<12) /* DRAM0 */
#define DSD1 (0<<14) /* DRAM1 */
#define DSD2 (0<<16) /* DRAM2 */
#define DSD3 (0<<18) /* DRAM3 */
#define DSX0 (0<<20) /* EXTIO0*/
#define DSX1 (1<<22) /* EXTIO1*/
#define DSX2 (1<<24) /* EXTIO2*/
#define DSX3 (1<<26) /* EXTIO3*/
/*#define rEXTDBWTH (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)*/
/* : deleted and added */
#define rEXTDBWTH 0x11110010
/* : added++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/*FLASH0*/
#define B0_Tacs 0x0 /*0clk*/
#define B0_Tcos 0x0 /*0clk*/
#define B0_Tacc 0x6 /*10clk*/
#define B0_Tcoh 0x0 /*0clk*/
#define B0_Tah 0x0 /*0clk*/
#define B0_Tacp 0x0 /*0clk*/
#define B0_PMC 0x0 /*normal(1data)*/
#define rROMCON0 ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
/*FLASH1*/
#define rROMCON1 rROMCON0
/*CPLD1 External (CF Card)*/
#define B2_Tacs 0x3 /*4clk*/
#define B2_Tcos 0x3 /*4clk*/
#define B2_Tacc 0x7 /*14clk*/
#define B2_Tcoh 0x3 /*4clk*/
#define B2_Tah 0x3 /*4clk*/
#define B2_Tacp 0x3 /*6clk*/
#define B2_PMC 0x0 /*normal(1data)*/
#define rROMCON2 ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
/*CPLD2 Exernal (Net)*/
#define rROMCON3 rROMCON2
/*CPLD3 USER FREE*/
#define rROMCON4 rROMCON2
/*CPLD4 Internal*/
#define rROMCON5 rROMCON2
/*SDRAM1 Bank 6 parameter*/
/*BDRAMTYPE="DRAM" ;MT=01(FP DRAM) or 10(EDO DRAM)*/
#define B6_MT 0x3 /*SDRAM*/
#define B6_Trcd 0x0 /*2clk*/
#define B6_SCAN 0x1 /*8bit*/
#define rSDRAMCON0 ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
/*SDRAM2 Bank 7 parameter*/
#define rSDRAMCON1 rSDRAMCON0
/*REFRESH parameter*/
#define REFEN 0x1 /*Refresh enable*/
#define TREFMD 0x0 /*CBR(CAS before RAS)/Auto refresh*/
#define Trp 0x2 /*3clk*/
#define Trc 0x1 /*5clk*/
#define Tchr 0x2 /*3clk*/
/*REFCNT = 2048 + 1 - MCLK(MHz) * 15.6*/
#define REFCNT 1050 /*period=15.6us, MCLK=66Mhz*/
#define rSREFEXTCON ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
#define rBANKSIZE 0x10 /*SCLK power down mode, BANKSIZE 32M/32M*/
#define rMRSRB6 0x20 /*MRSR6 CL=2clk*/
#define rMRSRB7 0x20 /*MRSR7*/
/*PLLCLK = 66000000
;Freq calc：
;Fout = (8+ M_DIV)*Fout/[(2+P_DIV)*2]
*/
#if (fMCLK_MHz == 40000000)
#define M_DIV 0x48
#define P_DIV 0x3
#define S_DIV 0x2
#endif
#if (fMCLK_MHz == 50000000)
#define M_DIV 0x2a
#define P_DIV 0x3
#define S_DIV 0x1
#endif
#if (fMCLK_MHz == 60000000)
#define M_DIV 0x34
#define P_DIV 0x3
#define S_DIV 0x1
#endif
#if (fMCLK_MHz == 75000000)
#define M_DIV 0x43
#define P_DIV 0x3
#define S_DIV 0x1
#endif
#define rPLLCON ((M_DIV<<12)+(P_DIV<<4)+S_DIV) /*Fin=10MHz,Fout=40MHz*/
#define rLOCKTIME 0xfff
/* : added++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* interrupt levels */ /* : 注意编号顺序,和4510相反,修改较多 */
#define INT_LVL_TIMER0 4 /* Timer 0 Interrupt */
#define INT_LVL_TIMER1 5 /* Timer 1 Interrupt */
#define INT_LVL_UART0 6 /* UART 0 Receive & Error Interrupt */
#define INT_LVL_UART1 7 /* UART 1 Receive & Error Interrupt */
#define INT_LVL_EXTINT0 14 /* External Interrupt0 */
#define INT_LVL_EXTINT1 15 /* External Interrupt1 */
#define INT_LVL_EXTINT2 16 /* External Interrupt2 */
#define INT_LVL_EXTINT3 17 /* External Interrupt3 */
#define INT_LVL_TICK 20
#define INT_LVL_ZDMA0 19
#define INT_LVL_ZDMA1 18
#define INT_LVL_BDMA0 17
#define INT_LVL_BDMA1 16
#define INT_LVL_WDT 15
#define INT_LVL_UERR01 14
#define INT_LVL_TIMER2 11
#define INT_LVL_TIMER3 10
#define INT_LVL_TIMER4 9
#define INT_LVL_TIMER5 8
#define INT_LVL_IIC 5
#define INT_LVL_SIO 4
#define INT_LVL_UARTTX0 3 /* UART 0 Transmit Interrupt */
#define INT_LVL_UARTTX1 2 /* UART 1 Transmit Interrupt */
#define INT_LVL_RTC 1
#define INT_LVL_ADC 0
/* interrupt vectors */
#define INT_VEC_EXTINT0 IVEC_TO_INUM(INT_LVL_EXTINT0) /* External Interrupt0 */
#define INT_VEC_EXTINT1 IVEC_TO_INUM(INT_LVL_EXTINT1) /* External Interrupt1*/
#define INT_VEC_EXTINT2 IVEC_TO_INUM(INT_LVL_EXTINT2) /* External Interrupt2*/
#define INT_VEC_EXTINT3 IVEC_TO_INUM(INT_LVL_EXTINT3) /* External Interrupt3*/
#define INT_VEC_UART0 IVEC_TO_INUM(INT_LVL_UART0) /* UART 0 Interrupt */
#define INT_VEC_UART1 IVEC_TO_INUM(INT_LVL_UART1) /* UART 1 Interrupt */
#define INT_VEC_TIMER0 IVEC_TO_INUM(INT_LVL_TIMER0) /* Timer 0 Interrupt */
#define INT_VEC_TIMER1 IVEC_TO_INUM(INT_LVL_TIMER1) /* Timer 1 Interrupt */
#define INT_VEC_IIC IVEC_TO_INUM(INT_LVL_IIC) /* IIC -Bus Interrupt */
/**********************************************************************************************************
* Cache Definitions
*
*/
#define SBCARM7_CACHE_0K (0<<1)
#define SBCARM7_CACHE_4K (1<<1)
#define SBCARM7_CACHE_8K (3<<1)
#define SBCARM7_WRITE_BUFF (1<<3)
#define SBCARM7_CACHE_MODE 0x0E
#define SBCARM7_CACHE_SIZE SBCARM7_CACHE_8K
#define NON_CACHE_REGION 0 /*TODO*/
/*#define SBCARM7_TAGRAM 0x11000000*/
#define SBCARM7_TAGRAM_BEG 0x10002000 /*CACHE TAG RAM起始地址*/
#define SBCARM7_TAGRAM_END 0x10004800 /*CACHE TAG RAM结束地址*/
/*
*
* definitions for the SBCARM7 Timer:
* two timers clocked from same source and with the same reload overhead
*/
#define SBCARM7_TIMER_SYS_TC_DISABLE (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_SYS_TC_ENABLE (TC_ENABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_AUX_TC_DISABLE (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM7_TIMER_AUX_TC_ENABLE (TC_ENABLE | TC_PERIODIC | TC_DIV16)
#define SYS_TIMER_CLK (fMCLK_MHz) /* Frequency of counter/timer */
#define AUX_TIMER_CLK (fMCLK_MHz) /* Frequency of counter/timer */
#define SBCARM7_RELOAD_TICKS 3 /* three ticks to reload timer */
#define SYS_TIMER_CLEAR(x) (SBCARM7_TIMER_T1CLEAR(x)) /* sys Clk is timer 1 */
#define SYS_TIMER_CTRL(x) (SBCARM7_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x) (SBCARM7_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x) (SBCARM7_TIMER_T1VALUE(x))
#define SBCARM7_TIMER_VALUE_MASK 0xFFFF
#define AUX_TIMER_CLEAR(x) (SBCARM7_TIMER_T2CLEAR(x)) /* aux Clk is timer 2 */
#define AUX_TIMER_CTRL(x) (SBCARM7_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x) (SBCARM7_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x) (SBCARM7_TIMER_T2VALUE(x))
#define SYS_TIMER_INT_LVL (INT_LVL_TIMER0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER1)
/******************************************************************************************
* Clock rates depend upon CPU power and work load of application.
* The values below are minimum and maximum allowed by the hardware.
* Note that it takes 3 ticks to reload the 16-bit counter and we don't
* accept values that would mean a zero reload value as we don't know what
* that will do.
* So:
* min frequency = roundup(clock_rate/(max_counter_value+3))
* max frequency = rounddown(clock_rate/(min_counter_value+3))
* i.e. SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4)
* However, we must set maxima that are sustainable on a running
* system. Experiments suggest that a 16MHz PID board can sustain a
* maximum clock rate of 10000 to 10500. The values below have been
* chosen so that there is a reasonable margin and the BSP passes the
* test suite.
*/
#define SYS_CLK_RATE_MIN 10
#define SYS_CLK_RATE_MAX 10000
#define AUX_CLK_RATE_MIN 2
#define AUX_CLK_RATE_MAX 10000
#define SBCARM7_RESET_RAM_BASE 0x1000000 RAM base in reset memory map */
/*
* Our MAC address definition. User can change this value as
* per requirement. Note, the least significant byte of the
* address is changed to the value of the user DIP switch setting.
* SW4-D0 is the least significant bit of this byte. Open=0.
*/
#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }
#ifdef __cplusplus
}
#endif
#endif /* INCsbcarm7h */
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