📄 i2c_pas106b.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY i2c_pas106b IS
PORT(
i2c_clk : IN STD_LOGIC; --1MHz
button_b : IN STD_LOGIC;
sda : INOUT STD_LOGIC;
scl : OUT STD_LOGIC;
clk_60 : OUT STD_LOGIC;
clk_220 : OUT STD_LOGIC --250HZ
);
END i2c_pas106b;
ARCHITECTURE a OF i2c_pas106b IS
type state is (idle,start,slv,adrs,data,ack1,ack2,ack3,stop,stop1,stop2);
signal now,nxt : state;
SIGNAL cnt1 : STD_LOGIC_vector(3 downto 0); -------- 62.5KHz
--SIGNAL cnt1 : STD_LOGIC_vector(4 downto 0); -------- 57.6KHz
--SIGNAL cnt1 : STD_LOGIC_vector(8 downto 0); -------- 58.6KHz
SIGNAL cnt2 : STD_LOGIC_vector(3 downto 0);
SIGNAL cnt3 : STD_LOGIC_vector(3 downto 0);
SIGNAL cnt4 : STD_LOGIC_vector(3 downto 0);
SIGNAL cnt_s : STD_LOGIC_vector(4 downto 0);
SIGNAL cnt_n : STD_LOGIC_vector(3 downto 0);
SIGNAL cnt_slv : STD_LOGIC_vector(3 downto 0);
SIGNAL cnt_ack : STD_LOGIC_vector(4 downto 0);
SIGNAL j : STD_LOGIC_vector(3 downto 0);
SIGNAL cntxx : STD_LOGIC_vector(1 downto 0);
SIGNAL en : STD_LOGIC;
SIGNAL cnt_snap : STD_LOGIC_vector(13 downto 0);
SIGNAL q : STD_LOGIC_vector(11 downto 0);
SIGNAL rst : STD_LOGIC;
SIGNAL oe : STD_LOGIC;
SIGNAL jp : STD_LOGIC;
SIGNAL clk_cnt : STD_LOGIC;
SIGNAL clk_dly : STD_LOGIC;
SIGNAL d1,d2,d3,d4 : STD_LOGIC;
SIGNAL scl_in : STD_LOGIC;
SIGNAL sda_in1,sda_in2,sda_in3 : STD_LOGIC;
SIGNAL s1,s2 : STD_LOGIC;
SIGNAL led : STD_LOGIC;
constant slavadrs : std_logic_vector(7 downto 0):="10000000";
constant num : std_logic_vector(3 downto 0):="1110";
SIGNAL addresst : std_logic_vector(7 downto 0);
SIGNAL datat : std_logic_vector(7 downto 0);
--------------------------------- address & data --------------------------------------
---------------------------------------------------------------------------------------
--------------------------------- PAS106BC test ---------------------------------------
constant address2 : std_logic_vector(7 downto 0):="00000010";
constant address3 : std_logic_vector(7 downto 0):="00000011";
constant address4 : std_logic_vector(7 downto 0):="00000100";
constant address5 : std_logic_vector(7 downto 0):="00000101";
constant address6 : std_logic_vector(7 downto 0):="00000110";
constant address7 : std_logic_vector(7 downto 0):="00000111";
constant address8 : std_logic_vector(7 downto 0):="00001000";
constant address9 : std_logic_vector(7 downto 0):="00001001";
constant address10 : std_logic_vector(7 downto 0):="00001010";
constant address11 : std_logic_vector(7 downto 0):="00001011";
constant address12 : std_logic_vector(7 downto 0):="00001100";
constant address13 : std_logic_vector(7 downto 0):="00001101";
constant address14 : std_logic_vector(7 downto 0):="00001110";
constant address17 : std_logic_vector(7 downto 0):="00010001";
constant address18 : std_logic_vector(7 downto 0):="00010010";
constant address19 : std_logic_vector(7 downto 0):="00010011";
constant data2 : std_logic_vector(7 downto 0):="00001010"; --Np=10
constant data3 : std_logic_vector(7 downto 0):="00001100"; --line_per_frm_H=12
constant data4 : std_logic_vector(7 downto 0):="00000101"; --line_per_frm_L=5
constant data5 : std_logic_vector(7 downto 0):="00100010"; --offset_ny=34
constant data6 : std_logic_vector(7 downto 0):="10000000"; --offset_nx=128
constant data7 : std_logic_vector(7 downto 0):="00000001"; --DAC_H=1
constant data8 : std_logic_vector(7 downto 0):="00110000"; --DAC_L=6 Reg_8[7:3]==>dac[4:0]
constant data9 : std_logic_vector(7 downto 0):="00000101"; --color_B=5
constant data10 : std_logic_vector(7 downto 0):="00001010"; --color_G1=0
constant data11 : std_logic_vector(7 downto 0):="00001111"; --color_G2=0
constant data12 : std_logic_vector(7 downto 0):="00001111"; --color_R=5
constant data13 : std_logic_vector(7 downto 0):="00001111"; --color_D=0
constant data14 : std_logic_vector(7 downto 0):="00001111"; --Global_gain=14
constant data17 : std_logic_vector(7 downto 0):="00000110"; --RSV=6
constant data18 : std_logic_vector(7 downto 0):="00000110"; --RSV=6
constant data19 : std_logic_vector(7 downto 0):="00000001"; --i2c_updata_sync_flag=1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
--------------------------------- PAS202BCA test ---------------------------------------
--constant address2 : std_logic_vector(7 downto 0):="00000010";--A2
--constant address3 : std_logic_vector(7 downto 0):="00000011";--A3
--constant address6 : std_logic_vector(7 downto 0):="00000110";--A6
--constant address7 : std_logic_vector(7 downto 0):="00000111";--A7
--constant address8 : std_logic_vector(7 downto 0):="00001000";--A8
--constant address9 : std_logic_vector(7 downto 0):="00001001";--A9
--constant address11 : std_logic_vector(7 downto 0):="00001011";--A11
--constant address12 : std_logic_vector(7 downto 0):="00001100";--A12
--constant address13 : std_logic_vector(7 downto 0):="00001101";--A13
--constant address14 : std_logic_vector(7 downto 0):="00001110";--A14
--constant address15 : std_logic_vector(7 downto 0):="00001111";--A15
--constant address16 : std_logic_vector(7 downto 0):="00010000";--A16
--constant address17 : std_logic_vector(7 downto 0):="00010001";--A17
--constant address19 : std_logic_vector(7 downto 0):="00010011";--A19
--constant address21 : std_logic_vector(7 downto 0):="00010101";--A21
-- sysclk = 48 MHz
--constant data2 : std_logic_vector(7 downto 0):="00001100"; --Np=12 ==>pixclk = 12 MHz
--constant data3 : std_logic_vector(7 downto 0):="01000000"; --Nov_by2=0x40=64
--constant data6 : std_logic_vector(7 downto 0):="00000000"; --cgn_dk=0
--constant data7 : std_logic_vector(7 downto 0):="00000000"; --cgn_B=0
--constant data8 : std_logic_vector(7 downto 0):="00000000"; --cgn_G=0
--constant data9 : std_logic_vector(7 downto 0):="00000000"; --cgn_R=0
--constant data11 : std_logic_vector(7 downto 0):="00000001"; --DAC[8]=1
--constant data12 : std_logic_vector(7 downto 0):="00000100"; --DAC[7:0]=4
--constant data13 : std_logic_vector(7 downto 0):="00101101"; --offset_ne_by4[7:0]=45
--constant data14 : std_logic_vector(7 downto 0):="00000001"; --offset_ny[0]=1
--constant data15 : std_logic_vector(7 downto 0):="00110000"; --offset_ny[8:1]=48
--constant data16 : std_logic_vector(7 downto 0):="00001010"; --global[4:0]=10
--constant data19 : std_logic_vector(7 downto 0):="00111111"; --RSV=63
--constant data21 : std_logic_vector(7 downto 0):="01000110"; --RSV=70
--constant data17 : std_logic_vector(7 downto 0):="00000001"; --i2c_updata_sync=1
---------------------------------------------------------------------------------------
BEGIN
sda <= sda_in1 when en='0' else -------------- deliver( SDA : OUT)
'Z';
sda_in2 <= sda when en='1' else -------------- receive( SDA : IN)
'Z';
process(i2c_clk,cnt1,button_b,cntxx,oe,s1,cnt_slv,clk_cnt,en)
begin
if button_b'event and button_b='1' then
cntxx <= cntxx+1;
if cntxx=1 then
cntxx <= "01";
end if;
end if;
if cntxx=0 then
oe <= '0';
else
oe <= '1';
end if;
if oe='1' then
if i2c_clk'event and i2c_clk='1' then
cnt1 <= cnt1+1;
cnt_snap <= cnt_snap+1;
now <= nxt;
if jp'event and jp='1' then
j <= j+1;
if j=num then
j <= num;
end if;
end if;
if j=0 then
addresst <= address2;
datat <= data2;
elsif j=1 then
addresst <= address5;
datat <= data5;
elsif j=2 then
addresst <= address6;
datat <= data6;
elsif j=3 then
addresst <= address7;
datat <= data7;
elsif j=4 then
addresst <= address8;
datat <= data8;
elsif j=5 then
addresst <= address9;
datat <= data9;
elsif j=6 then
addresst <= address10;
datat <= data10;
elsif j=7 then
addresst <= address11;
datat <= data11;
elsif j=8 then
addresst <= address12;
datat <= data12;
elsif j=9 then
addresst <= address13;
datat <= data13;
elsif j=10 then
addresst <= address14;
datat <= data14;
elsif j=11 then
addresst <= address17;
datat <= data17;
elsif j=12 then
addresst <= address18;
datat <= data18;
elsif j=13 then
addresst <= address19;
datat <= data19;
end if;
end if;
if i2c_clk'event and i2c_clk='1' then
d1 <= clk_cnt;
d2 <= d1;
d3 <= d2;
d4 <= d3;
end if;
if s1='1' then
if i2c_clk'event and i2c_clk='1' then
cnt_slv <= cnt_slv+1;
end if;
if cnt_slv =8 then
cnt_slv <= cnt_slv;
-- cnt_slv <= "0000";
if clk_cnt'event and clk_cnt='1' then --
cnt_n <= cnt_n+1;
end if;
end if;
else
cnt_n <= "0000";
cnt_slv <= "0000";
end if;
if en='1' then
--if s2='1' then
if i2c_clk'event and i2c_clk='1' then
cnt_ack <= cnt_ack+1;
if cnt_ack=15 then
cnt_ack <= "00000";
end if;
end if;
else
cnt_ack <= "00000";
end if;
end if;
end process;
clk_dly <= d4;
process(i2c_clk,cnt_s,now,clk_dly,cnt_n,sda_in2,cnt_ack,addresst,datat,oe)
begin
en <= '0';
sda_in3 <= '0';
s1 <= '0';
s2 <= '0';
jp <= '0';
led <= '0';
if oe='1' then
case now is
when idle =>
sda_in1 <= '1';
scl_in <= '1';
nxt <= start;
cnt_s <= "00000";
when start =>
if i2c_clk'event and i2c_clk='1' then
cnt_s <= cnt_s+1;
if (cnt_s<16) then
sda_in1 <= '1';
scl_in <= '1';
nxt <= start;
elsif cnt_s=31 then
cnt_s <= cnt_s;
sda_in1 <= '0';
scl_in <= '0'; ---1
nxt <= slv;
else
sda_in1 <= '0';
scl_in <= '1';
nxt <= start; --
end if;
end if;
when slv =>
s1 <= '1';
scl_in <= clk_dly;
if cnt_n=0 then
sda_in1 <= '0';
scl_in <= '0';
nxt <= slv;
elsif cnt_n=1 then
sda_in1 <= slavadrs(7);
nxt <= slv;
elsif cnt_n=2 then
sda_in1 <= slavadrs(6);
nxt <= slv;
elsif cnt_n=3 then
sda_in1 <= slavadrs(5);
nxt <= slv;
elsif cnt_n=4 then
sda_in1 <= slavadrs(4);
nxt <= slv;
elsif cnt_n=5 then
sda_in1 <= slavadrs(3);
nxt <= slv;
elsif cnt_n=6 then
sda_in1 <= slavadrs(2);
nxt <= slv;
elsif cnt_n=7 then
sda_in1 <= slavadrs(1);
nxt <= slv;
elsif cnt_n=8 then
sda_in1 <= slavadrs(0);
nxt <= slv;
elsif cnt_n=9 then
en <= '1';
-- if sda_in2='0' then
--led <= '1';
if cnt_ack=15 then
nxt <= ack1;
else
sda_in1 <= '1';
scl_in <= '1';
end if;
-- else
--nxt <= ack1; ---stop1
-- end if;
end if;
when ack1 =>
sda_in1 <= '0';
scl_in <= '0';
nxt <= adrs;
when adrs =>
s1 <= '1';
scl_in <= clk_dly;
if cnt_n=0 then
sda_in1 <= '0';
scl_in <= '0';
nxt <= adrs;
elsif cnt_n=1 then
sda_in1 <= addresst(7);
nxt <= adrs;
elsif cnt_n=2 then
sda_in1 <= addresst(6);
nxt <= adrs;
elsif cnt_n=3 then
sda_in1 <= addresst(5);
nxt <= adrs;
elsif cnt_n=4 then
sda_in1 <= addresst(4);
nxt <= adrs;
elsif cnt_n=5 then
sda_in1 <= addresst(3);
nxt <= adrs;
elsif cnt_n=6 then
sda_in1 <= addresst(2);
nxt <= adrs;
elsif cnt_n=7 then
sda_in1 <= addresst(1);
nxt <= adrs;
elsif cnt_n=8 then
sda_in1 <= addresst(0);
nxt <= adrs;
elsif cnt_n=9 then
en <= '1';
--if sda_in2='0' then --⌨️ 快捷键说明
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