altivec.igen

这个是LINUX下的GDB调度工具的源码

	  else
	    (*vS).b[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.838:VXR:av:vcmpgtshx %VD, %VA, %VB:Vector Compare Greater-Than Signed Half Word
	int i;
	signed16 a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  if (a > b)
	    (*vS).h[i] = 0xffff;
	  else
	    (*vS).h[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.902:VXR:av:vcmpgtswx %VD, %VA, %VB:Vector Compare Greater-Than Signed Word
	int i;
	signed32 a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  if (a > b)
	    (*vS).w[i] = 0xffffffff;
	  else
	    (*vS).w[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.518:VXR:av:vcmpgtubx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Byte
	int i;
	unsigned8 a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  if (a > b)
	    (*vS).b[i] = 0xff;
	  else
	    (*vS).b[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.582:VXR:av:vcmpgtuhx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Half Word
	int i;
	unsigned16 a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  if (a > b)
	    (*vS).h[i] = 0xffff;
	  else
	    (*vS).h[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.646:VXR:av:vcmpgtuwx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Word
	int i;
	unsigned32 a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  if (a > b)
	    (*vS).w[i] = 0xffffffff;
	  else
	    (*vS).w[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

#
# Vector Convert instructions, 6-65, 6-66.
#

0.4,6.VS,11.UIMM,16.VB,21.970:VX:av:vctsxs %VD, %VB, %UIMM:Vector Convert to Signed Fixed-Point Word Saturate
	int i, sat, tempsat;
	signed64 temp;
	sim_fpu a, b, m;
	sat = 0;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_u32to (&m, 2 << UIMM, sim_fpu_round_default);
	  sim_fpu_mul (&a, &b, &m);
	  sim_fpu_to64i (&temp, &a, sim_fpu_round_default);
	  (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.UIMM,16.VB,21.906:VX:av:vctuxs %VD, %VB, %UIMM:Vector Convert to Unsigned Fixed-Point Word Saturate
	int i, sat, tempsat;
	signed64 temp;
	sim_fpu a, b, m;
	sat = 0;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_u32to (&m, 2 << UIMM, sim_fpu_round_default);
	  sim_fpu_mul (&a, &b, &m);
	  sim_fpu_to64u (&temp, &a, sim_fpu_round_default);
	  (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK);

#
# Vector Estimate instructions, 6-67 ... 6-70.
#

0.4,6.VS,11.0,16.VB,21.394:VX:av:vexptefp %VD, %VB:Vector 2 Raised to the Exponent Estimate Floating Point
	int i;
	unsigned32 f;
	signed32 bi;
	sim_fpu b, d;
	for (i = 0; i < 4; i++) {
	  /*HACK!*/
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_to32i (&bi, &b, sim_fpu_round_default);
	  bi = 2 ^ bi;
	  sim_fpu_32to (&d, bi);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.0,16.VB,21.458:VX:av:vlogefp %VD, %VB:Vector Log2 Estimate Floating Point
	int i;
	unsigned32 c, u, f;
	sim_fpu b, cfpu, d;
	for (i = 0; i < 4; i++) {
	  /*HACK!*/
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_to32u (&u, &b, sim_fpu_round_default);
	  for (c = 0; (u /= 2) > 1; c++)
	    ;
	  sim_fpu_32to (&cfpu, c);
	  sim_fpu_add (&d, &b, &cfpu);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK);

#
# Vector Multiply Add instruction, 6-71
#

0.4,6.VS,11.VA,16.VB,21.VC,26.46:VAX:av:vmaddfp %VD, %VA, %VB, %VC:Vector Multiply Add Floating Point
	int i;
	unsigned32 f;
	sim_fpu a, b, c, d, e;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_32to (&c, (*vC).w[i]);
	  sim_fpu_mul (&e, &a, &c);
	  sim_fpu_add (&d, &e, &b);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);


#
# Vector Maximum instructions, 6-72 ... 6-78.
#

0.4,6.VS,11.VA,16.VB,21.1034:VX:av:vmaxfp %VD, %VA, %VB:Vector Maximum Floating Point
	int i;
	unsigned32 f;
	sim_fpu a, b, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_max (&d, &a, &b);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.258:VX:av:vmaxsb %VD, %VA, %VB:Vector Maximum Signed Byte
	int i;
	signed8 a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  if (a > b)
	    (*vS).b[i] = a;
	  else
	    (*vS).b[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.322:VX:av:vmaxsh %VD, %VA, %VB:Vector Maximum Signed Half Word
	int i;
	signed16 a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  if (a > b)
	    (*vS).h[i] = a;
	  else
	    (*vS).h[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.386:VX:av:vmaxsw %VD, %VA, %VB:Vector Maximum Signed Word
	int i;
	signed32 a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  if (a > b)
	    (*vS).w[i] = a;
	  else
	    (*vS).w[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.2:VX:av:vmaxub %VD, %VA, %VB:Vector Maximum Unsigned Byte
	int i;
	unsigned8 a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  if (a > b)
	    (*vS).b[i] = a;
	  else
	    (*vS).b[i] = b;
	};
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.66:VX:av:vmaxus %VD, %VA, %VB:Vector Maximum Unsigned Half Word
	int i;
	unsigned16 a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  if (a > b)
	    (*vS).h[i] = a;
	  else
	    (*vS).h[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.130:VX:av:vmaxuw %VD, %VA, %VB:Vector Maximum Unsigned Word
	int i;
	unsigned32 a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  if (a > b)
	    (*vS).w[i] = a;
	  else
	    (*vS).w[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Multiple High instructions, 6-79, 6-80.
#

0.4,6.VS,11.VA,16.VB,21.VC,26.32:VAX:av:vmhaddshs %VD, %VA, %VB, %VC:Vector Multiple High and Add Signed Half Word Saturate
	int i, sat, tempsat;
	signed16 a, b;
	signed32 prod, temp, c;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  c = (signed32)(signed16)(*vC).h[i];
	  prod = (signed32)a * (signed32)b;
	  temp = (prod >> 15) + c;
	  (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

0.4,6.VS,11.VA,16.VB,21.VC,26.33:VAX:av:vmhraddshs %VD, %VA, %VB, %VC:Vector Multiple High Round and Add Signed Half Word Saturate
	int i, sat, tempsat;
	signed16 a, b;
	signed32 prod, temp, c;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  c = (signed32)(signed16)(*vC).h[i];
	  prod = (signed32)a * (signed32)b;
	  prod += 0x4000;
	  temp = (prod >> 15) + c;
	  (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);


#
# Vector Minimum instructions, 6-81 ... 6-87
#

0.4,6.VS,11.VA,16.VB,21.1098:VX:av:vminfp %VD, %VA, %VB:Vector Minimum Floating Point
	int i;
	unsigned32 f;
	sim_fpu a, b, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_min (&d, &a, &b);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.770:VX:av:vminsb %VD, %VA, %VB:Vector Minimum Signed Byte
	int i;
	signed8 a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  if (a < b)
	    (*vS).b[i] = a;
	  else
	    (*vS).b[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.834:VX:av:vminsh %VD, %VA, %VB:Vector Minimum Signed Half Word
	int i;
	signed16 a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  if (a < b)
	    (*vS).h[i] = a;
	  else
	    (*vS).h[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.898:VX:av:vminsw %VD, %VA, %VB:Vector Minimum Signed Word
	int i;
	signed32 a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  if (a < b)
	    (*vS).w[i] = a;
	  else
	    (*vS).w[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.514:VX:av:vminub %VD, %VA, %VB:Vector Minimum Unsigned Byte
	int i;
	unsigned8 a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  if (a < b)
	    (*vS).b[i] = a;
	  else
	    (*vS).b[i] = b;
	};
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.578:VX:av:vminuh %VD, %VA, %VB:Vector Minimum Unsigned Half Word
	int i;
	unsigned16 a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  if (a < b)
	    (*vS).h[i] = a;
	  else
	    (*vS).h[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.642:VX:av:vminuw %VD, %VA, %VB:Vector Minimum Unsigned Word
	int i;
	unsigned32 a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  if (a < b)
	    (*vS).w[i] = a;
	  else
	    (*vS).w[i] = b;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Multiply Low instruction, 6-88
#

0.4,6.VS,11.VA,16.VB,21.VC,26.34:VAX:av:vmladduhm %VD, %VA, %VB, %VC:Vector Multiply Low and Add Unsigned Half Word Modulo
	int i;
	unsigned16 a, b, c;
	unsigned32 prod;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  c = (*vC).h[i];
	  prod = (unsigned32)a * (unsigned32)b;
	  (*vS).h[i] = (prod + c) & 0xffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);


#
# Vector Merge instructions, 6-89 ... 6-94
#

0.4,6.VS,11.VA,16.VB,21.12:VX:av:vmrghb %VD, %VA, %VB:Vector Merge High Byte
	int i;
	for (i = 0; i < 16; i += 2) {
	  (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i/2)];
	  (*vS).b[AV_BINDEX(i+1)] = (*vB).b[AV_BINDEX(i/2)]; 
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.76:VX:av:vmrghh %VD, %VA, %VB:Vector Merge High Half Word
	int i;
	for (i = 0; i < 8; i += 2) {
	  (*vS).h[AV_HINDEX(i)] = (*vA).h[AV_HINDEX(i/2)];
	  (*vS).h[AV_HINDEX(i+1)] = (*vB).h[AV_HINDEX(i/2)]; 
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.140:VX:av:vmrghw %VD, %VA, %VB:Vector Merge High Word
	int i;
	for (i = 0; i < 4; i += 2) {
	  (*vS).w[i] = (*vA).w[i/2];
	  (*vS).w[i+1] = (*vB).w[i/2]; 
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.268:VX:av:vmrglb %VD, %VA, %VB:Vector Merge Low Byte
	int i;