vm.c

这个是LINUX下的GDB调度工具的源码

/*  This file is part of the program psim.

    Copyright (C) 1994-1997, Andrew Cagney <[e-mail]>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
    */


#ifndef _VM_C_
#define _VM_C_

#if 0
#include "basics.h"
#include "registers.h"
#include "device.h"
#include "corefile.h"
#include "vm.h"
#include "interrupts.h"
#include "mon.h"
#endif

#include "cpu.h"

/* OEA vs VEA

   For the VEA model, the VM layer is almost transparent.  It's only
   purpose is to maintain separate core_map's for the instruction
   and data address spaces.  This being so that writes to instruction
   space or execution of a data space is prevented.

   For the OEA model things are more complex.  The reason for separate
   instruction and data models becomes crucial.  The OEA model is
   built out of three parts.  An instruction map, a data map and an
   underlying structure that provides access to the VM data kept in
   main memory. */


/* OEA data structures:

   The OEA model maintains internal data structures that shadow the
   semantics of the various OEA VM registers (BAT, SR, etc).  This
   allows a simple efficient model of the VM to be implemented.

   Consistency between OEA registers and this model's internal data
   structures is maintained by updating the structures at
   `synchronization' points.  Of particular note is that (at the time
   of writing) the memory data types for BAT registers are rebuilt
   when ever the processor moves between problem and system states.

   Unpacked values are stored in the OEA so that they correctly align
   to where they will be needed by the PTE address. */


/* Protection table:

   Matrix of processor state, type of access and validity */

typedef enum {
  om_supervisor_state,
  om_problem_state,
  nr_om_modes
} om_processor_modes;

typedef enum {
  om_data_read, om_data_write,
  om_instruction_read, om_access_any,
  nr_om_access_types
} om_access_types;

static int om_valid_access[2][4][nr_om_access_types] = {
  /* read, write, instruction, any */
  /* K bit == 0 */
  { /*r  w  i  a       pp */
    { 1, 1, 1, 1 }, /* 00 */
    { 1, 1, 1, 1 }, /* 01 */
    { 1, 1, 1, 1 }, /* 10 */
    { 1, 0, 1, 1 }, /* 11 */
  },
  /* K bit == 1  or P bit valid */
  { /*r  w  i  a       pp */
    { 0, 0, 0, 0 }, /* 00 */
    { 1, 0, 1, 1 }, /* 01 */
    { 1, 1, 1, 1 }, /* 10 */
    { 1, 0, 1, 1 }, /* 11 */
  }
};


/* Bat translation:

   The bat data structure only contains information on valid BAT
   translations for the current processor mode and type of access. */

typedef struct _om_bat {
  unsigned_word block_effective_page_index;
  unsigned_word block_effective_page_index_mask;
  unsigned_word block_length_mask;
  unsigned_word block_real_page_number;
  int protection_bits;
} om_bat;

enum _nr_om_bat_registers {
  nr_om_bat_registers = 4
};

typedef struct _om_bats {
  int nr_valid_bat_registers;
  om_bat bat[nr_om_bat_registers];
} om_bats;


/* Segment TLB:

   In this model the 32 and 64 bit segment tables are treated in very
   similar ways.  The 32bit segment registers are treated as a
   simplification of the 64bit segment tlb */

enum _om_segment_tlb_constants {
#if (WITH_TARGET_WORD_BITSIZE == 64)
  sizeof_segment_table_entry_group = 128,
  sizeof_segment_table_entry = 16,
#endif
  om_segment_tlb_index_start_bit = 32,
  om_segment_tlb_index_stop_bit = 35,
  nr_om_segment_tlb_entries = 16,
  nr_om_segment_tlb_constants
};

typedef struct _om_segment_tlb_entry {
  int key[nr_om_modes];
  om_access_types invalid_access; /* set to instruction if no_execute bit */
  unsigned_word masked_virtual_segment_id; /* aligned ready for pte group addr */
#if (WITH_TARGET_WORD_BITSIZE == 64)
  int is_valid;
  unsigned_word masked_effective_segment_id;
#endif
} om_segment_tlb_entry;

typedef struct _om_segment_tlb {
  om_segment_tlb_entry entry[nr_om_segment_tlb_entries];
} om_segment_tlb;


/* Page TLB:

   This OEA model includes a small direct map Page TLB.  The tlb is to
   cut down on the need for the OEA to perform walks of the page hash
   table. */

enum _om_page_tlb_constants {
  om_page_tlb_index_start_bit = 46,
  om_page_tlb_index_stop_bit = 51,
  nr_om_page_tlb_entries = 64,
#if (WITH_TARGET_WORD_BITSIZE == 64)
  sizeof_pte_group = 128,
  sizeof_pte = 16,
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
  sizeof_pte_group = 64,
  sizeof_pte = 8,
#endif
  nr_om_page_tlb_constants
};

typedef struct _om_page_tlb_entry {
  int protection;
  int changed;
  unsigned_word real_address_of_pte_1;
  unsigned_word masked_virtual_segment_id;
  unsigned_word masked_page;
  unsigned_word masked_real_page_number;
} om_page_tlb_entry;

typedef struct _om_page_tlb {
  om_page_tlb_entry entry[nr_om_page_tlb_entries];
} om_page_tlb;


/* memory translation:

   OEA memory translation possibly involves BAT, SR, TLB and HTAB
   information*/

typedef struct _om_map {

  /* local cache of register values */
  int is_relocate;
  int is_problem_state;

  /* block address translation */
  om_bats *bat_registers;

  /* failing that, translate ea to va using segment tlb */
#if (WITH_TARGET_WORD_BITSIZE == 64)
  unsigned_word real_address_of_segment_table;
#endif
  om_segment_tlb *segment_tlb;

  /* then va to ra using hashed page table and tlb */
  unsigned_word real_address_of_page_table;
  unsigned_word page_table_hash_mask;
  om_page_tlb *page_tlb;

  /* physical memory for fetching page table entries */
  core_map *physical;

  /* address xor for PPC endian */
  unsigned xor[WITH_XOR_ENDIAN];

} om_map;


/* VM objects:

   External objects defined by vm.h */

struct _vm_instruction_map {
  /* real memory for last part */
  core_map *code;
  /* translate effective to real */
  om_map translation;
};

struct _vm_data_map {
  /* translate effective to real */
  om_map translation;
  /* real memory for translated address */
  core_map *read;
  core_map *write;
};


/* VM:

   Underlying memory object.  For the VEA this is just the
   core_map. For OEA it is the instruction and data memory
   translation's */

struct _vm {

  /* OEA: base address registers */
  om_bats ibats;
  om_bats dbats;

  /* OEA: segment registers */
  om_segment_tlb segment_tlb;

  /* OEA: translation lookaside buffers */
  om_page_tlb instruction_tlb;
  om_page_tlb data_tlb;

  /* real memory */
  core *physical;

  /* memory maps */
  vm_instruction_map instruction_map;
  vm_data_map data_map;

};


/* OEA Support procedures */


STATIC_INLINE_VM\
(unsigned_word)
om_segment_tlb_index(unsigned_word ea)
{
  unsigned_word index = EXTRACTED(ea,
				  om_segment_tlb_index_start_bit,
				  om_segment_tlb_index_stop_bit);
  return index;
}

STATIC_INLINE_VM\
(unsigned_word)
om_page_tlb_index(unsigned_word ea)
{
  unsigned_word index = EXTRACTED(ea,
				  om_page_tlb_index_start_bit,
				  om_page_tlb_index_stop_bit);
  return index;
}

STATIC_INLINE_VM\
(unsigned_word)
om_hash_page(unsigned_word masked_vsid,
	     unsigned_word ea)
{
  unsigned_word extracted_ea = EXTRACTED(ea, 36, 51);
#if (WITH_TARGET_WORD_BITSIZE == 32)
  unsigned_word masked_ea = INSERTED32(extracted_ea, 7, 31-6);
  unsigned_word hash = masked_vsid ^ masked_ea;
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
  unsigned_word masked_ea = INSERTED64(extracted_ea, 18, 63-7);
  unsigned_word hash = masked_vsid ^ masked_ea;
#endif
  TRACE(trace_vm, ("ea=0x%lx - masked-vsid=0x%lx masked-ea=0x%lx hash=0x%lx\n",
		   (unsigned long)ea,
		   (unsigned long)masked_vsid,
		   (unsigned long)masked_ea,
		   (unsigned long)hash));
  return hash;
}

STATIC_INLINE_VM\
(unsigned_word)
om_pte_0_api(unsigned_word pte_0)
{
#if (WITH_TARGET_WORD_BITSIZE == 32)
  return EXTRACTED32(pte_0, 26, 31);
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
  return EXTRACTED64(pte_0, 52, 56);
#endif
}

STATIC_INLINE_VM\
(unsigned_word)
om_pte_0_hash(unsigned_word pte_0)
{
#if (WITH_TARGET_WORD_BITSIZE == 32)
  return EXTRACTED32(pte_0, 25, 25);
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
  return EXTRACTED64(pte_0, 62, 62);
#endif
}

STATIC_INLINE_VM\
(int)
om_pte_0_valid(unsigned_word pte_0)
{
#if (WITH_TARGET_WORD_BITSIZE == 32)
  return MASKED32(pte_0, 0, 0) != 0;
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
  return MASKED64(pte_0, 63, 63) != 0;
#endif
}

STATIC_INLINE_VM\
(unsigned_word)
om_ea_masked_page(unsigned_word ea)
{
  return MASKED(ea, 36, 51);
}

STATIC_INLINE_VM\
(unsigned_word)
om_ea_masked_byte(unsigned_word ea)
{
  return MASKED(ea, 52, 63);
}

/* return the VSID aligned for pte group addr */
STATIC_INLINE_VM\
(unsigned_word)
om_pte_0_masked_vsid(unsigned_word pte_0)
{
#if (WITH_TARGET_WORD_BITSIZE == 32)
  return INSERTED32(EXTRACTED32(pte_0, 1, 24), 31-6-24+1, 31-6);
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
  return INSERTED64(EXTRACTED64(pte_0, 0, 51), 63-7-52+1, 63-7);
#endif
}

STATIC_INLINE_VM\
(unsigned_word)
om_pte_1_pp(unsigned_word pte_1)
{
  return MASKED(pte_1, 62, 63); /*PP*/
}

STATIC_INLINE_VM\
(int)
om_pte_1_referenced(unsigned_word pte_1)
{
  return EXTRACTED(pte_1, 55, 55);
}

STATIC_INLINE_VM\
(int)
om_pte_1_changed(unsigned_word pte_1)
{