e500.igen

这个是LINUX下的GDB调度工具的源码

	t1 = a * b;
	t2 = ACC + t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);


0.4,6.RS,11.RA,16.RB,21.1455:EVX:e500:evmhogsmfan %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate Negative
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_LOHALF(*rA);
	b = (signed32)(signed16)EV_LOHALF(*rB);
	t1 = EV_MUL16_SSF(a, b);
	if (t1 & ((unsigned64)1 << 32))
	  t1 |= 0xfffffffe00000000;
	t2 = ACC - t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1453:EVX:e500:evmhogsmian %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate Negative
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_LOHALF(*rA);
	b = (signed32)(signed16)EV_LOHALF(*rB);
	t1 = (signed64)a * (signed64)b;
	t2 = ACC - t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
		//printf("evmhogsmian: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2);
		//printf("evmhogsmian: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1452:EVX:e500:evmhogumian %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative
	unsigned32 a, b;
	unsigned64 t1, t2;
	a = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	b = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	t1 = (unsigned64)a * (unsigned64)b;
	t2 = ACC - t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1451:EVX:e500:evmhegsmfan %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate Negative
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_HIHALF(*rA);
	b = (signed32)(signed16)EV_HIHALF(*rB);
	t1 = EV_MUL16_SSF(a, b);
	if (t1 & ((unsigned64)1 << 32))
	  t1 |= 0xfffffffe00000000;
	t2 = ACC - t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1449:EVX:e500:evmhegsmian %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate Negative
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_HIHALF(*rA);
	b = (signed32)(signed16)EV_HIHALF(*rB);
	t1 = (signed64)a * (signed64)b;
	t2 = ACC - t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1448:EVX:e500:evmhegumian %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate Negative
	unsigned32 a, b;
	unsigned64 t1, t2;
	a = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	b = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	t1 = (unsigned64)a * (unsigned64)b;
	t2 = ACC - t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);


0.4,6.RS,11.RA,16.RB,21.1095:EVX:e500:evmwhssf %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	int movl, movh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_ssf(al, bl, &movl);
	t2 = ev_multiply32_ssf(ah, bh, &movh);
	EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32),
			       EV_SATURATE(movl, 0x7fffffff, t1 >> 32));
	EV_SET_SPEFSCR_OV(movl, movh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1127:EVX:e500:evmwhssfa %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional and Accumulate
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	int movl, movh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_ssf(al, bl, &movl);
	t2 = ev_multiply32_ssf(ah, bh, &movh);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32),
			           EV_SATURATE(movl, 0x7fffffff, t1 >> 32));
	EV_SET_SPEFSCR_OV(movl, movh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1103:EVX:e500:evmwhsmf %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = EV_MUL32_SSF(al, bl);
	t2 = EV_MUL32_SSF(ah, bh);
	EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
	
0.4,6.RS,11.RA,16.RB,21.1135:EVX:e500:evmwhsmfa %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional and Accumulate
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = EV_MUL32_SSF(al, bl);
	t2 = EV_MUL32_SSF(ah, bh);
	EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1101:EVX:e500:evmwhsmi %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (signed64)al * (signed64)bl;
	t2 = (signed64)ah * (signed64)bh;
	EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1133:EVX:e500:evmwhsmia %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer and Accumulate
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (signed64)al * (signed64)bl;
	t2 = (signed64)ah * (signed64)bh;
	EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1100:EVX:e500:evmwhumi %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (unsigned64)al * (unsigned64)bl;
	t2 = (unsigned64)ah * (unsigned64)bh;
	EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1132:EVX:e500:evmwhumia %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer and Accumulate
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (unsigned64)al * (unsigned64)bl;
	t2 = (unsigned64)ah * (unsigned64)bh;
	EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);


0.4,6.RS,11.RA,16.RB,21.1091:EVX:e500:evmwlssf %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	int movl, movh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_ssf(al, bl, &movl);
	t2 = ev_multiply32_ssf(ah, bh, &movh);
	EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2),
			       EV_SATURATE(movl, 0xffffffff, t1));
	EV_SET_SPEFSCR_OV(movl, movh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1123:EVX:e500:evmwlssfa %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	int movl, movh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_ssf(al, bl, &movl);
	t2 = ev_multiply32_ssf(ah, bh, &movh);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2),
			           EV_SATURATE(movl, 0xffffffff, t1));
	EV_SET_SPEFSCR_OV(movl, movh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1099:EVX:e500:evmwlsmf %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = EV_MUL32_SSF(al, bl);
	t2 = EV_MUL32_SSF(ah, bh);
	EV_SET_REG2(*rSh, *rS, t2, t1);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1131:EVX:e500:evmwlsmfa %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = EV_MUL32_SSF(al, bl);
	t2 = EV_MUL32_SSF(ah, bh);
	EV_SET_REG2_ACC(*rSh, *rS, t2, t1);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1096:EVX:e500:evmwlumi %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (unsigned64)al * (unsigned64)bl;
	t2 = (unsigned64)ah * (unsigned64)bh;
	EV_SET_REG2(*rSh, *rS, t2, t1);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1128:EVX:e500:evmwlumia %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (unsigned64)al * (unsigned64)bl;
	t2 = (unsigned64)ah * (unsigned64)bh;
	EV_SET_REG2_ACC(*rSh, *rS, t2, t1);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);


0.4,6.RS,11.RA,16.RB,21.1347:EVX:e500:evmwlssfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate in Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int movl, movh, ovl, ovh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_ssf(ah, bh, &movh);
	t2 = ev_multiply32_ssf(al, bl, &movl);
	th = EV_ACCHIGH + EV_SATURATE(movh, 0xffffffff, t1);
	tl = EV_ACCLOW + EV_SATURATE(movl, 0xffffffff, t2);
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1345:EVX:e500:evmwlssiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate in Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int ovl, ovh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (signed64)ah * (signed64)bh;
	t2 = (signed64)al * (signed64)bl;
	th = EV_ACCHIGH + (t1 & 0xffffffff);
	tl = EV_ACCLOW + (t2 & 0xffffffff);
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1355:EVX:e500:evmwlsmfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate in Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	int mov;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_smf(ah, bh, &mov);
	t2 = ev_multiply32_smf(al, bl, &mov);
	EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff),
				 EV_ACCLOW + (t2 & 0xffffffff));
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1353:EVX:e500:evmwlsmiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate in Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (signed64)ah * (signed64)bh;
	t2 = (signed64)al * (signed64)bl;
	EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff),
				 EV_ACCLOW + (t2 & 0xffffffff));
		//printf("evmwlsmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd\n", al, ah, bl, bh, t1, t2);
		//printf("evmwlsmiaaw: *rSh = %08x; *rS = %08x\n", *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1344:EVX:e500:evmwlusiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2, tl, th;
	int ovl, ovh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (unsigned64)ah * (unsigned64)bh;
	t2 = (unsigned64)al * (unsigned64)bl;
	th = EV_ACCHIGH + (t1 & 0xffffffff);
	tl = EV_ACCLOW + (t2 & 0xffffffff);
	ovh = (th >> 32);
	ovl = (tl >> 32);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th),
			           EV_SATURATE(ovl, 0xffffffff, tl));
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1352:EVX:e500:evmwlumiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = (unsigned64)ah * (unsigned64)bh;
	t2 = (unsigned64)al * (unsigned64)bl;
	EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff),
				 EV_ACCLOW + (t2 & 0xffffffff));
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);


0.4,6.RS,11.RA,16.RB,21.1475:EVX:e500:evmwlssfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate Negative in Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int movl, movh, ovl, ovh;
	al = *rA;
	ah = *rAh;
	bl = *rB;
	bh = *rBh;
	t1 = ev_multiply32_ssf(ah, bh, &movh);
	t2 = ev_multiply32_ssf(al, bl, &movl);
	th = EV_ACCHIGH - EV_SATURATE(movh, 0xffffffff, t1);
	tl = EV_ACCLOW - EV_SATURATE(movl, 0xffffffff, t2);
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, s