e500.igen

这个是LINUX下的GDB调度工具的源码

	bh = (signed16) EV_HIHALF (*rBh);
	t1 = ev_multiply16_ssf (ah, bh, &movh);
	t2 = ev_multiply16_ssf (al, bl, &movl);
	th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1);
	tl = EV_ACCLOW  + EV_SATURATE (movl, 0x7fffffff, t2);
	ovh = EV_SAT_P_S32 (th);
	ovl = EV_SAT_P_S32 (tl);
	EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th),
			            EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int ovl, ovh;
	al = (signed32)(signed16)EV_HIHALF(*rA);
	ah = (signed32)(signed16)EV_HIHALF(*rAh);
	bl = (signed32)(signed16)EV_HIHALF(*rB);
	bh = (signed32)(signed16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
		//printf("evmhessiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmhessiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words
	signed16 al, ah, bl, bh;
	signed32 t1, t2, th, tl;
	int dummy;

	al = (signed16)EV_HIHALF(*rA);
	ah = (signed16)EV_HIHALF(*rAh);
	bl = (signed16)EV_HIHALF(*rB);
	bh = (signed16)EV_HIHALF(*rBh);
	t1 = ev_multiply16_smf (ah, bh, &dummy);
	t2 = ev_multiply16_smf (al, bl, &dummy);
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	EV_SET_REG2_ACC(*rSh, *rS, th, tl);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1289:EVX:e500:evmhesmiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (signed32)(signed16)EV_HIHALF(*rA);
	ah = (signed32)(signed16)EV_HIHALF(*rAh);
	bl = (signed32)(signed16)EV_HIHALF(*rB);
	bh = (signed32)(signed16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1280:EVX:e500:evmheusiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate into Words
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	signed64 tl, th;
	int ovl, ovh;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = (signed64)EV_ACCHIGH + (signed64)t1;
	tl = (signed64)EV_ACCLOW + (signed64)t2;
	ovh = EV_SAT_P_U32(th);
	ovl = EV_SAT_P_U32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl));
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1288:EVX:e500:evmheumiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate into Words
	unsigned32 al, ah, bl, bh;
	unsigned32 t1, t2;
	unsigned64 tl, th;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);


0.4,6.RS,11.RA,16.RB,21.1415:EVX:e500:evmhossfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words
	signed16 al, ah, bl, bh;
	signed32 t1, t2;
	signed64 tl, th;
	int movl, movh, ovl, ovh;
	
	al = (signed16) EV_LOHALF (*rA);
	ah = (signed16) EV_LOHALF (*rAh);
	bl = (signed16) EV_LOHALF (*rB);
	bh = (signed16) EV_LOHALF (*rBh);
	t1 = ev_multiply16_ssf (ah, bh, &movh);
	t2 = ev_multiply16_ssf (al, bl, &movl);
	th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1);
	tl = EV_ACCLOW  - EV_SATURATE (movl, 0x7fffffff, t2);
	ovh = EV_SAT_P_S32 (th);
	ovl = EV_SAT_P_S32 (tl);
	EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th),
			            EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1413:EVX:e500:evmhossianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate Negative into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int ovl, ovh;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH - t1;
	tl = EV_ACCLOW - t2;
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV(ovl, ovh);
		//printf("evmhossianw: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1423:EVX:e500:evmhosmfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate Negative into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	t1 = ((signed64)ah * bh) << 1;
	t2 = ((signed64)al * bl) << 1;
	th = EV_ACCHIGH - (t1 & 0xffffffff);
	tl = EV_ACCLOW - (t2 & 0xffffffff);
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1421:EVX:e500:evmhosmianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH - t1;
	tl = EV_ACCLOW - t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1412:EVX:e500:evmhousianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate Negative into Words
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	signed64 tl, th;
	int ovl, ovh;
	al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = (signed64)EV_ACCHIGH - (signed64)t1;
	tl = (signed64)EV_ACCLOW - (signed64)t2;
	ovl = EV_SAT_P_U32(tl);
	ovh = EV_SAT_P_U32(th);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl));
		//printf("evmhousianw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmoussianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1420:EVX:e500:evmhoumianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words
	unsigned32 al, ah, bl, bh;
	unsigned32 t1, t2;
	unsigned64 tl, th;
	al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH - t1;
	tl = EV_ACCLOW - t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1411:EVX:e500:evmhessfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words
	signed16 al, ah, bl, bh;
	signed32 t1, t2;
	signed64 tl, th;
	int movl, movh, ovl, ovh;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);
	bh = (signed16) EV_HIHALF (*rBh);
	t1 = ev_multiply16_ssf (ah, bh, &movh);
	t2 = ev_multiply16_ssf (al, bl, &movl);
	th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1);
	tl = EV_ACCLOW  - EV_SATURATE (movl, 0x7fffffff, t2);
	ovh = EV_SAT_P_S32 (th);
	ovl = EV_SAT_P_S32 (tl);
	EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th),
			            EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1409:EVX:e500:evmhessianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate Negative into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int ovl, ovh;
	al = (signed32)(signed16)EV_HIHALF(*rA);
	ah = (signed32)(signed16)EV_HIHALF(*rAh);
	bl = (signed32)(signed16)EV_HIHALF(*rB);
	bh = (signed32)(signed16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH - t1;
	tl = EV_ACCLOW - t2;
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1419:EVX:e500:evmhesmfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	t1 = ((signed64)ah * bh) << 1;
	t2 = ((signed64)al * bl) << 1;
	th = EV_ACCHIGH - (t1 & 0xffffffff);
	tl = EV_ACCLOW - (t2 & 0xffffffff);
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1417:EVX:e500:evmhesmianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate Negative into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (signed32)(signed16)EV_HIHALF(*rA);
	ah = (signed32)(signed16)EV_HIHALF(*rAh);
	bl = (signed32)(signed16)EV_HIHALF(*rB);
	bh = (signed32)(signed16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH - t1;
	tl = EV_ACCLOW - t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
		//printf("evmhesmianw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmhesmianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1408:EVX:e500:evmheusianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate Negative into Words
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	signed64 tl, th;
	int ovl, ovh;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = (signed64)EV_ACCHIGH - (signed64)t1;
	tl = (signed64)EV_ACCLOW - (signed64)t2;
	ovl = EV_SAT_P_U32(tl);
	ovh = EV_SAT_P_U32(th);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl));
		//printf("evmheusianw: ovh %d ovl %d al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmheusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1416:EVX:e500:evmheumianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate Negative into Words
	unsigned32 al, ah, bl, bh;
	unsigned32 t1, t2;
	unsigned64 tl, th;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH - t1;
	tl = EV_ACCLOW - t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1327:EVX:e500:evmhogsmfaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_LOHALF(*rA);
	b = (signed32)(signed16)EV_LOHALF(*rB);
	t1 = EV_MUL16_SSF(a, b);
	if (t1 & ((unsigned64)1 << 32))
	  t1 |= 0xfffffffe00000000;
	t2 = ACC + t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1325:EVX:e500:evmhogsmiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_LOHALF(*rA);
	b = (signed32)(signed16)EV_LOHALF(*rB);
	t1 = (signed64)a * (signed64)b;
	t2 = (signed64)ACC + t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
		//printf("evmhogsmiaa: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2);
		//printf("evmhogsmiaa: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1324:EVX:e500:evmhogumiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate
	unsigned32 a, b;
	unsigned64 t1, t2;
	a = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	b = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	t1 = a * b;
	t2 = ACC + t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1323:EVX:e500:evmhegsmfaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_HIHALF(*rA);
	b = (signed32)(signed16)EV_HIHALF(*rB);
	t1 = EV_MUL16_SSF(a, b);
	if (t1 & ((unsigned64)1 << 32))
	  t1 |= 0xfffffffe00000000;
	t2 = ACC + t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1321:EVX:e500:evmhegsmiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate
	signed32 a, b;
	signed64 t1, t2;
	a = (signed32)(signed16)EV_HIHALF(*rA);
	b = (signed32)(signed16)EV_HIHALF(*rB);
	t1 = (signed64)(a * b);
	t2 = ACC + t1;
	EV_SET_REG1_ACC(*rSh, *rS, t2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1320:EVX:e500:evmhegumiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate
	unsigned32 a, b;
	unsigned64 t1, t2;
	a = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	b = (unsigned32)(unsigned16)EV_HIHALF(*rB);