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这个是LINUX下的GDB调度工具的源码

	  ch = 1;
	else
	  ch = 0;
	if (al == bl)
	  cl = 1;
	else
	  cl = 0;
	w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl);
	CR_SET(BF, w);
		//printf("evcmpeq: ch %d cl %d BF %d, CR is now %08x\n", ch, cl, BF, CR);
	PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);

0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select
	unsigned32 w1, w2;
	int cr;
	cr = CR_FIELD(CRFS);
	if (cr & 8)
	  w1 = *rAh;
	else
	  w1 = *rBh;
	if (cr & 4)
	  w2 = *rA;
	else
	  w2 = *rB;
	EV_SET_REG2(*rSh, *rS, w1, w2);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment
	unsigned32 w1, w2, a, d, mask;
	mask = (*rB) & 0xffff;
	a = (*rA) & 0xffff;
	d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask));
	*rS = ((*rA) & 0xffff0000) | (d & 0xffff);
		//printf("brinc: *rS = %08x\n", *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

#
# A.2.8 Integer SPE Complex Instructions
#

0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	int movl, movh;
	
	al = (signed16) EV_LOHALF (*rA);
	ah = (signed16) EV_LOHALF (*rAh);
	bl = (signed16) EV_LOHALF (*rB);
	bh = (signed16) EV_LOHALF (*rBh);
	tl = ev_multiply16_ssf (al, bl, &movl);
	th = ev_multiply16_ssf (ah, bh, &movh);
	EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
			        EV_SATURATE (movl, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl, movh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	int movl, movh;
	
	al = (signed16) EV_LOHALF (*rA);
	ah = (signed16) EV_LOHALF (*rAh);
	bl = (signed16) EV_LOHALF (*rB);
	bh = (signed16) EV_LOHALF (*rBh);
	tl = ev_multiply16_ssf (al, bl, &movl);
	th = ev_multiply16_ssf (ah, bh, &movh);
	EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
			        EV_SATURATE (movl, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl, movh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	int dummy;
	
	al = (signed16) EV_LOHALF (*rA);
	ah = (signed16) EV_LOHALF (*rAh);
	bl = (signed16) EV_LOHALF (*rB);
	bh = (signed16) EV_LOHALF (*rBh);
	tl = ev_multiply16_smf (al, bl, & dummy);
	th = ev_multiply16_smf (ah, bh, & dummy);
	EV_SET_REG2 (*rSh, *rS, th, tl);
	PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate
	signed32 al, ah, bl, bh;
	signed32 tl, th;
	int dummy;
	
	al = (signed16) EV_LOHALF (*rA);
	ah = (signed16) EV_LOHALF (*rAh);
	bl = (signed16) EV_LOHALF (*rB);
	bh = (signed16) EV_LOHALF (*rBh);
	tl = ev_multiply16_smf (al, bl, & dummy);
	th = ev_multiply16_smf (ah, bh, & dummy);
	EV_SET_REG2_ACC (*rSh, *rS, th, tl);
	PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer
	signed32 al, ah, bl, bh, tl, th;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2(*rSh, *rS, th, tl);
		//printf("evmhosmi: *rSh = %08x; *rS = %08x\n", *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate
	signed32 al, ah, bl, bh, tl, th;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2_ACC(*rSh, *rS, th, tl);
		//printf("evmhosmia: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer
	unsigned32 al, ah, bl, bh, tl, th;
	al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2(*rSh, *rS, th, tl);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate
	unsigned32 al, ah, bl, bh, tl, th;
	al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2_ACC(*rSh, *rS, th, tl);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	int movl, movh;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);
	bh = (signed16) EV_HIHALF (*rBh);
	tl = ev_multiply16_ssf (al, bl, &movl);
	th = ev_multiply16_ssf (ah, bh, &movh);
	EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
			       EV_SATURATE (movl, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl, movh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	int movl, movh;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);
	bh = (signed16) EV_HIHALF (*rBh);
	tl = ev_multiply16_ssf (al, bl, &movl);
	th = ev_multiply16_ssf (ah, bh, &movh);
	EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
				    EV_SATURATE (movl, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl, movh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional
	signed16 al, ah, bl, bh;
	signed64 tl, th;
	int movl, movh;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);
	bh = (signed16) EV_HIHALF (*rBh);
	tl = ev_multiply16_smf (al, bl, &movl);
	th = ev_multiply16_smf (ah, bh, &movh);
	EV_SET_REG2 (*rSh, *rS, th, tl);
	EV_SET_SPEFSCR_OV (movl, movh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	int dummy;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);
	bh = (signed16) EV_HIHALF (*rBh);
	tl = ev_multiply16_smf (al, bl, & dummy);
	th = ev_multiply16_smf (ah, bh, & dummy);
	EV_SET_REG2_ACC (*rSh, *rS, th, tl);
	PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer
	signed16 al, ah, bl, bh;
	signed32 tl, th;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);
	bh = (signed16) EV_HIHALF (*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2 (*rSh, *rS, th, tl);
	PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate
	signed32 al, ah, bl, bh, tl, th;
	al = (signed32)(signed16)EV_HIHALF(*rA);
	ah = (signed32)(signed16)EV_HIHALF(*rAh);
	bl = (signed32)(signed16)EV_HIHALF(*rB);
	bh = (signed32)(signed16)EV_HIHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2_ACC(*rSh, *rS, th, tl);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer
	unsigned32 al, ah, bl, bh, tl, th;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2(*rSh, *rS, th, tl);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate
	unsigned32 al, ah, bl, bh, tl, th;
	al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
	tl = al * bl;
	th = ah * bh;
	EV_SET_REG2_ACC(*rSh, *rS, th, tl);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words
	signed16 al, ah, bl, bh;
	signed32 t1, t2;
	signed64 tl, th;
	int movl, movh, ovl, ovh;
	
	al = (signed16) EV_LOHALF (*rA);
	ah = (signed16) EV_LOHALF (*rAh);
	bl = (signed16) EV_LOHALF (*rB);
	bh = (signed16) EV_LOHALF (*rBh);
	t1 = ev_multiply16_ssf (ah, bh, &movh);
	t2 = ev_multiply16_ssf (al, bl, &movl);
	th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1);
	tl = EV_ACCLOW  + EV_SATURATE (movl, 0x7fffffff, t2);
	ovh = EV_SAT_P_S32 (th);
	ovl = EV_SAT_P_S32 (tl);
	EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th),
			            EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl));
	EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh);
	PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	int ovl, ovh;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	ovh = EV_SAT_P_S32(th);
	ovl = EV_SAT_P_S32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl));
		//printf("evmhossiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmhossiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	t1 = ((signed64)ah * bh) << 1;
	t2 = ((signed64)al * bl) << 1;
	th = EV_ACCHIGH + (t1 & 0xffffffff);
	tl = EV_ACCLOW + (t2 & 0xffffffff);
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words
	signed32 al, ah, bl, bh;
	signed64 t1, t2, tl, th;
	al = (signed32)(signed16)EV_LOHALF(*rA);
	ah = (signed32)(signed16)EV_LOHALF(*rAh);
	bl = (signed32)(signed16)EV_LOHALF(*rB);
	bh = (signed32)(signed16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
		//printf("evmhosmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmhosmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words
	unsigned32 al, ah, bl, bh;
	unsigned64 t1, t2;
	signed64 tl, th;
	int ovl, ovh;
	al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = (signed64)EV_ACCHIGH + (signed64)t1;
	tl = (signed64)EV_ACCLOW + (signed64)t2;
	ovh = EV_SAT_P_U32(th);
	ovl = EV_SAT_P_U32(tl);
	EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
			           EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl));
		//printf("evmhousiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmhousiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	EV_SET_SPEFSCR_OV(ovl, ovh);
	PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words
	unsigned32 al, ah, bl, bh;
	unsigned32 t1, t2;
	signed64 tl, th;
	al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
	ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
	bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
	bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
	t1 = ah * bh;
	t2 = al * bl;
	th = EV_ACCHIGH + t1;
	tl = EV_ACCLOW + t2;
	EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
		//printf("evmhoumiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th);
		//printf("evmhoumiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
	PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words
	signed16 al, ah, bl, bh;
	signed32 t1, t2;
	signed64 tl, th;
	int movl, movh, ovl, ovh;
	
	al = (signed16) EV_HIHALF (*rA);
	ah = (signed16) EV_HIHALF (*rAh);
	bl = (signed16) EV_HIHALF (*rB);