ppc-instructions

这个是LINUX下的GDB调度工具的源码

# handle case of invalid operation
void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 fra, unsigned64 frb, int single
	if (FPSCR & fpscr_ze) {
	  /* zero-divide exception enabled */
	  /* FRT unchaged */
	  FPSCR_SET_FR(0);
	  FPSCR_SET_FI(0);
	  /* fpscr_FPRF unchanged */
	}
	else {
	  /* zero-divide exception disabled */
	  FPSCR_SET_FR(0);
	  FPSCR_SET_FI(0);
	  if ((sign (fra) < 0 && sign (frb) < 0)
	      || (sign (fra) > 0 && sign (frb) > 0)) {
	    *frt = MASK64 (1, 11); /* 0 : 2047 : 0..0 */
	    FPSCR_SET_FPRF(fpscr_rf_pos_infinity);
	  }
	  else {
	    *frt = MASK64 (0, 11); /* 1 : 2047 : 0..0 */
	    FPSCR_SET_FPRF(fpscr_rf_neg_infinity);
	  }
	}





#
# 0.0.0.0 Illegal instruction used for kernel mode emulation
#
0.0,6./,11./,16./,21./,31.1:X:::instruction_call
	if (!os_emul_instruction_call(processor, cia, real_addr(cia, 1)))
	  program_interrupt(processor, cia,
	                    illegal_instruction_program_interrupt);

#
# I.2.4.1 Branch Instructions
#
0.18,6.LI,30.AA,31.LK:I:::Branch
*601: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603e:PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	/* option_mpc860c0:
	No problem here because this branch is predicted taken (unconditional). */
	if (AA) NIA = IEA(EXTS(LI_0b00));
	else    NIA = IEA(CIA + EXTS(LI_0b00));
	if (LK) LR = (spreg)CIA+4;
	if (CURRENT_MODEL_ISSUE > 0)
	  model_branches(cpu_model(processor), 1, -1);

0.16,6.BO,11.BI,16.BD,30.AA,31.LK:B:::Branch Conditional
*601: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603e:PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	int M, ctr_ok, cond_ok, succeed;
	if (CURRENT_MODEL_ISSUE > 0 && ! BO{0})
	  model_wait_for_cr(cpu_model(processor), BIT32_BI);
	if (is_64bit_implementation && is_64bit_mode) M = 0;
	else                                          M = 32;
	if (!BO{2}) CTR = CTR - 1;
	ctr_ok = BO{2} || ((MASKED(CTR, M, 63) != 0) != (BO{3}));
	cond_ok = BO{0} || ((CR{BI}) == (BO{1}));
	if (ctr_ok && cond_ok) {
	  if (AA) NIA = IEA(EXTS(BD_0b00));
	  else    NIA = IEA(CIA + EXTS(BD_0b00));
	  succeed = 1;
	}
	else
	  succeed = 0;
	if (LK) LR = (spreg)IEA(CIA + 4);
	if (option_mpc860c0 && (!BO{0} || !BO{2}) && !BO{4}) {
	  /* This branch is predicted as "normal".
	  If this is a forward branch and it is near the end of a page,
	  we've detected a problematic branch. */
	  if (succeed && NIA > CIA) {
	    if (PAGE_SIZE - (CIA & (PAGE_SIZE-1)) <= option_mpc860c0)
	      program_interrupt(processor, cia, mpc860c0_instruction_program_interrupt);
	  }
	}
	if (CURRENT_MODEL_ISSUE > 0)
	  model_branches(cpu_model(processor), succeed, BO);
	if (! BO{0}) {
	  int reverse;
	  if (BO{4}) {	/* branch prediction bit set, reverse sense of test */
	    reverse = EXTS(BD_0b00) < 0;
	  } else {	/* branch prediction bit not set */
	    reverse = EXTS(BD_0b00) >= 0;
	  }
	  if (CURRENT_MODEL_ISSUE > 0)
	    model_branch_predict(cpu_model(processor), reverse ? !succeed : succeed);
	}

0.19,6.BO,11.BI,16./,21.16,31.LK:XL:::Branch Conditional to Link Register
*601: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603e:PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	int M, ctr_ok, cond_ok, succeed;
	if (is_64bit_implementation && is_64bit_mode) M = 0;
	else                                          M = 32;
	if (CURRENT_MODEL_ISSUE > 0 && ! BO{0})
	  model_wait_for_cr(cpu_model(processor), BIT32_BI);
	if (!BO{2}) CTR = CTR - 1;
	ctr_ok = BO{2} || ((MASKED(CTR, M, 63) != 0) != BO{3});
	cond_ok = BO{0} || (CR{BI} == BO{1});
	if (ctr_ok && cond_ok) {
	  NIA = IEA(LR_0b00);
	  succeed = 1;
	}
	else
	  succeed = 0;
	if (LK) LR = (spreg)IEA(CIA + 4);
	if (option_mpc860c0 && (!BO{0} || !BO{2}) && !BO{4}) {
	  /* This branch is predicted as not-taken.
	  If this is a forward branch and it is near the end of a page,
	  we've detected a problematic branch. */
	  if (succeed && NIA > CIA) {
	    if (PAGE_SIZE - (CIA & (PAGE_SIZE-1)) <= option_mpc860c0)
	      program_interrupt(processor, cia, mpc860c0_instruction_program_interrupt);
	  }
	}
	if (CURRENT_MODEL_ISSUE > 0) {
	  model_branches(cpu_model(processor), succeed, BO);
	  if (! BO{0})
	    model_branch_predict(cpu_model(processor), BO{4} ? !succeed : succeed);
	}

0.19,6.BO,11.BI,16./,21.528,31.LK:XL:::Branch Conditional to Count Register
*601: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*603e:PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	int cond_ok, succeed;
	if (CURRENT_MODEL_ISSUE > 0 && ! BO{0})
	  model_wait_for_cr(cpu_model(processor), BIT32_BI);
	cond_ok = BO{0} || (CR{BI} == BO{1});
	if (cond_ok) {
	  NIA = IEA(CTR_0b00);
	  succeed = 1;
	}
	else
	  succeed = 0;
	if (LK) LR = (spreg)IEA(CIA + 4);
	if (option_mpc860c0 && (!BO{0} || !BO{2}) && !BO{4}) {
	  /* This branch is predicted as not-taken.
	  If this is a forward branch and it is near the end of a page,
	  we've detected a problematic branch. */
	  if (succeed && NIA > CIA) {
	    if (PAGE_SIZE - (CIA & (PAGE_SIZE-1)) <= option_mpc860c0)
	      program_interrupt(processor, cia, mpc860c0_instruction_program_interrupt);
	  }
	}
	if (CURRENT_MODEL_ISSUE > 0) {
	  model_branches(cpu_model(processor), succeed, BO);
	  if (! BO{0})
	    model_branch_predict(cpu_model(processor), BO{4} ? !succeed : succeed);
	}

#
# I.2.4.2 System Call Instruction
#
0.17,6./,11./,16./,30.1,31./:SC:::System Call
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   3,  3,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   3,  3,  0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1,  1,  0
	if (CURRENT_MODEL_ISSUE > 0)
	  model_serialize(MY_INDEX, cpu_model(processor));
	system_call_interrupt(processor, cia);

#
# I.2.4.3 Condition Register Logical Instructions
#
0.19,6.BT,11.BA,16.BB,21.257,31./:XL::crand:Condition Register AND
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, CR{BA} && CR{BB});
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.449,31./:XL::cror:Condition Register OR
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, CR{BA} || CR{BB});
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.193,31./:XL::crxor:Condition Register XOR
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, CR{BA} != CR{BB});
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.225,31./:XL::crnand:Condition Register NAND
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, !(CR{BA} && CR{BB}));
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.33,31./:XL::crnor:Condition Register NOR
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, !(CR{BA} || CR{BB}));
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.289,31./:XL::creqv:Condition Register Equivalent
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, CR{BA} == CR{BB});
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.129,31./:XL::crandc:Condition Register AND with Complement
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, CR{BA} && !CR{BB});
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

0.19,6.BT,11.BA,16.BB,21.417,31./:XL::crorc:Condition Register OR with Complement
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	BLIT32(CR, BT, CR{BA} || !CR{BB});
	PPC_INSN_CR(BT_BITMASK, BA_BITMASK | BB_BITMASK);

#
# I.2.4.4 Condition Register Field Instruction
#
0.19,6.BF,9./,11.BFA,14./,16./,21.0,31./:XL:::Move Condition Register Field
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  1,  0
*603: PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*603e:PPC_UNIT_SRU,   PPC_UNIT_SRU,   1,  1,  0
*604: PPC_UNIT_BPU,   PPC_UNIT_BPU,   1,  1,  0
	MBLIT32(CR, 4*BF, 4*BF+3, EXTRACTED32(CR, 4*BFA, 4*BFA+3));
	PPC_INSN_CR(BF_BITMASK, 1 << BFA);


#
# I.3.3.2 Fixed-Point Load Instructions
#

0.34,6.RT,11.RA,16.D:D:::Load Byte and Zero
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = b + EXTS(D);
	*rT = MEM(unsigned, EA, 1);
	PPC_INSN_INT(RT_BITMASK, (RA_BITMASK & ~1), 0);


0.31,6.RT,11.RA,16.RB,21.87,31./:X:::Load Byte and Zero Indexed
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = b + *rB;
	*rT = MEM(unsigned, EA, 1);
	PPC_INSN_INT(RT_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0);

0.35,6.RT,11.RA,16.D:D:::Load Byte and Zero with Update
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word EA;
	if (RA_is_0 || RA == RT)
	  program_interrupt(processor, cia,
	                    illegal_instruction_program_interrupt);
	EA = *rA + EXTS(D);
	*rT = MEM(unsigned, EA, 1);
	*rA = EA;
	PPC_INSN_INT(RT_BITMASK | RA_BITMASK, RA_BITMASK, 0);

0.31,6.RT,11.RA,16.RB,21.119,31./:X:::Load Byte and Zero with Update Indexed
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word EA;
	if (RA_is_0 || RA == RT)
	  program_interrupt(processor, cia,
	                    illegal_instruction_program_interrupt);
	EA = *rA + *rB;
	*rT = MEM(unsigned, EA, 1);
	*rA = EA;
	PPC_INSN_INT(RT_BITMASK | RA_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.40,6.RT,11.RA,16.D:D:::Load Halfword and Zero
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = b + EXTS(D);
	*rT = MEM(unsigned, EA, 2);
	PPC_INSN_INT(RT_BITMASK, (RA_BITMASK & ~1), 0);

0.31,6.RT,11.RA,16.RB,21.279,31./:X:::Load Halfword and Zero Indexed
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = b + *rB;
	*rT = MEM(unsigned, EA, 2);
	PPC_INSN_INT(RT_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0);

0.41,6.RT,11.RA,16.D:D:::Load Halfword and Zero with Update
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word EA;
	if (RA_is_0 || RA == RT)
	  program_interrupt(processor, cia,
	                    illegal_instruction_program_interrupt);
	EA = *rA + EXTS(D);
	*rT = MEM(unsigned, EA, 2);
	*rA = EA;
	PPC_INSN_INT(RT_BITMASK | RA_BITMASK, RA_BITMASK, 0);

0.31,6.RT,11.RA,16.RB,21.311,31./:X:::Load Halfword and Zero with Update Indexed
*601: PPC_UNIT_IU,    PPC_UNIT_IU,    1,  2,  0
*603: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*603e:PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
*604: PPC_UNIT_LSU,   PPC_UNIT_LSU,   1,  2,  0
	unsigned_word EA;
	if (RA_is_0 || RA == RT)
	  program_interrupt(proce