hw_phb.c

这个是LINUX下的GDB调度工具的源码

/*  This file is part of the program psim.

    Copyright (C) 1994-1996, Andrew Cagney <[e-mail]>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
    */


#ifndef _HW_PHB_C_
#define _HW_PHB_C_

#include "device_table.h"

#include "hw_phb.h"

#include "corefile.h"

#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif

#include <ctype.h>


/* DEVICE


   phb - PCI Host Bridge


   DESCRIPTION


   PHB implements a model of the PCI-host bridge described in the PPCP
   document.

   For bridge devices, Open Firmware specifies that the <<ranges>>
   property be used to specify the mapping of address spaces between a
   bridges parent and child busses.  This PHB model configures itsself
   according to the information specified in its ranges property.  The
   <<ranges>> property is described in detail in the Open Firmware
   documentation.

   For DMA transfers, any access to a PCI address space which falls
   outside of the mapped memory space is assumed to be a transfer
   intended for the parent bus.


   PROPERTIES


   ranges = <my-phys-addr> <parent-phys-addr> <my-size> ...  (required)
   
   Define a number of mappings from the parent bus to one of this
   devices PCI busses.  The exact format of the <<parent-phys-addr>>
   is parent bus dependant.  The format of <<my-phys-addr>> is
   described in the Open Firmware PCI bindings document (note that the
   address must be non-relocatable).


   #address-cells = 3  (required)

   Number of cells used by an Open Firmware PCI address.  This
   property must be defined before specifying the <<ranges>> property.


   #size-cells = 2  (required)

   Number of cells used by an Open Firmware PCI size.  This property
   must be defined before specifying the <<ranges>> property.


   EXAMPLES
   

   Enable tracing:

   |  $ psim \
   |    -t phb-device \


   Since device tree entries that are specified on the command line
   are added before most of the device tree has been built it is often
   necessary to explictly add certain device properties and thus
   ensure they are already present in the device tree.  For the
   <<phb>> one such property is parent busses <<#address-cells>>.

   |    -o '/#address-cells 1' \


   Create the PHB remembering to include the cell size properties:
   
   |    -o '/phb@0x80000000/#address-cells 3' \
   |    -o '/phb@0x80000000/#size-cells 2' \


   Specify that the memory address range <<0x80000000>> to
   <<0x8fffffff>> should map directly onto the PCI memory address
   space while the processor address range <<0xc0000000>> to
   <<0xc000ffff>> should map onto the PCI I/O address range starting
   at location zero:

   |    -o '/phb@0x80000000/ranges \
   |                nm0,0,0,80000000 0x80000000 0x10000000 \
   |                ni0,0,0,0 0xc0000000 0x10000' \


   Insert a 4k <<nvram>> into slot zero of the PCI bus.  Have it
   directly accessible in both the I/O (address <<0x100>>) and memory
   (address 0x80001000) spaces:

   |    -o '/phb@0x80000000/nvram@0/assigned-addresses \
   |                nm0,0,10,80001000 4096 \
   |                ni0,0,14,100 4096'
   |    -o '/phb@0x80000000/nvram@0/reg \
   |                0 0 \
   |                i0,0,14,0 4096'
   |    -o '/phb@0x80000000/nvram@0/alternate-reg \
   |                0 0 \
   |                m0,0,10,0 4096'

   The <<assigned-address>> property corresponding to what (if it were
   implemented) be found in the config base registers while the
   <<reg>> and <<alternative-reg>> properties indicating the location
   of registers within each address space.

   Of the possible addresses, only the non-relocatable versions are
   used when attaching the device to the bus.


   BUGS
   

   The implementation of the PCI configuration space is left as an
   exercise for the reader.  Such a restriction should only impact on
   systems wanting to dynamically configure devices on the PCI bus.

   The <<CHRP>> document specfies additional (optional) functionality
   of the primary PHB. The implementation of such functionality is
   left as an exercise for the reader.

   The Open Firmware PCI bus bindings document (rev 1.6 and 2.0) is
   unclear on the value of the "ss" bits for a 64bit memory address.
   The correct value, as used by this module, is 0b11.
   
   The Open Firmware PCI bus bindings document (rev 1.6) suggests that
   the register field of non-relocatable PCI address should be zero.
   Unfortunatly, PCI addresses specified in the <<assigned-addresses>>
   property must be both non-relocatable and have non-zero register
   fields.

   The unit-decode method is not inserting a bus number into any
   address that it decodes.  Instead the bus-number is left as zero.

   Support for aliased memory and I/O addresses is left as an exercise
   for the reader.

   Support for interrupt-ack and special cycles are left as an
   exercise for the reader.  One issue to consider when attempting
   this exercise is how to specify the address of the int-ack and
   special cycle register.  Hint: <</8259-interrupt-ackowledge>> is
   the wrong answer.

   Children of this node can only use the client callback interface
   when attaching themselves to the <<phb>>.

   
   REFERENCES


   http://playground.sun.com/1275/home.html#OFDbusPCI


   */

   
typedef struct _phb_space {
  core *map;
  core_map *readable;
  core_map *writeable;
  unsigned_word parent_base;
  int parent_space;
  unsigned_word my_base;
  int my_space;
  unsigned size;	
  const char *name;
} phb_space;

typedef struct _hw_phb_device  {
  phb_space space[nr_hw_phb_spaces];
} hw_phb_device;


static const char *
hw_phb_decode_name(hw_phb_decode level)
{
  switch (level) {
  case hw_phb_normal_decode: return "normal";
  case hw_phb_subtractive_decode: return "subtractive";
  case hw_phb_master_abort_decode: return "master-abort";
  default: return "invalid decode";
  }
}


static void
hw_phb_init_address(device *me)
{
  hw_phb_device *phb = device_data(me);
 
  /* check some basic properties */
  if (device_nr_address_cells(me) != 3)
    device_error(me, "incorrect #address-cells");
  if (device_nr_size_cells(me) != 2)
    device_error(me, "incorrect #size-cells");

  /* (re) initialize each PCI space */
  {
    hw_phb_spaces space_nr;
    for (space_nr = 0; space_nr < nr_hw_phb_spaces; space_nr++) {
      phb_space *pci_space = &phb->space[space_nr];
      core_init(pci_space->map);
      pci_space->size = 0;
    }
  }

  /* decode each of the ranges properties entering the information
     into the space table */
  {
    range_property_spec range;
    int ranges_entry;
    
    for (ranges_entry = 0;
	 device_find_range_array_property(me, "ranges", ranges_entry,
					  &range);
	 ranges_entry++) {
      int my_attach_space;
      unsigned_word my_attach_address;
      int parent_attach_space;
      unsigned_word parent_attach_address;
      unsigned size;
      phb_space *pci_space;
      /* convert the addresses into something meaningful */
      device_address_to_attach_address(me, &range.child_address,
				       &my_attach_space,
				       &my_attach_address,
				       me);
      device_address_to_attach_address(device_parent(me),
				       &range.parent_address,
				       &parent_attach_space,
				       &parent_attach_address,
				       me);
      device_size_to_attach_size(me, &range.size, &size, me);
      if (my_attach_space < 0 || my_attach_space >= nr_hw_phb_spaces)
	device_error(me, "ranges property contains an invalid address space");
      pci_space = &phb->space[my_attach_space];
      if (pci_space->size != 0)
	device_error(me, "ranges property contains duplicate mappings for %s address space",
		     pci_space->name);
      pci_space->parent_base = parent_attach_address;
      pci_space->parent_space = parent_attach_space;
      pci_space->my_base = my_attach_address;
      pci_space->my_space = my_attach_space;
      pci_space->size = size;
      device_attach_address(device_parent(me),
			    attach_callback,
			    parent_attach_space, parent_attach_address, size,
			    access_read_write_exec,
			    me);
      DTRACE(phb, ("map %d:0x%lx to %s:0x%lx (0x%lx bytes)\n",
		   (int)parent_attach_space,
		   (unsigned long)parent_attach_address,
		   pci_space->name,
		   (unsigned long)my_attach_address,
		   (unsigned long)size));
    }
    
    if (ranges_entry == 0) {
      device_error(me, "Missing or empty ranges property");
    }

  }
  
}

static void
hw_phb_attach_address(device *me,
		      attach_type type,
		      int space,
		      unsigned_word addr,
		      unsigned nr_bytes,
		      access_type access,
		      device *client) /*callback/default*/
{
  hw_phb_device *phb = device_data(me);
  phb_space *pci_space;
  /* sanity checks */
  if (space < 0 || space >= nr_hw_phb_spaces)
    device_error(me, "attach space (%d) specified by %s invalid",
		 space, device_path(client));
  pci_space = &phb->space[space];
  if (addr + nr_bytes > pci_space->my_base + pci_space->size
      || addr < pci_space->my_base)
    device_error(me, "attach addr (0x%lx) specified by %s outside of bus address range",
		 (unsigned long)addr, device_path(client));
  if (type != hw_phb_normal_decode
      && type != hw_phb_subtractive_decode)
    device_error(me, "attach type (%d) specified by %s invalid",
		 type, device_path(client));
  /* attach it to the relevent bus */
  DTRACE(phb, ("attach %s - %s %s:0x%lx (0x%lx bytes)\n",
	       device_path(client),
	       hw_phb_decode_name(type),
	       pci_space->name,
	       (unsigned long)addr,
	       (unsigned long)nr_bytes));
  core_attach(pci_space->map,
	      type,
	      space,
	      access,
	      addr,
	      nr_bytes,
	      client);
}


/* Extract/set various fields from a PCI unit address.

   Note: only the least significant 32 bits of each cell is used.

   Note: for PPC MSB is 0 while for PCI it is 31. */


/* relocatable bit n */

static unsigned
extract_n(const device_unit *address)
{
  return EXTRACTED32(address->cells[0], 0, 0);
}

static void
set_n(device_unit *address)
{
  BLIT32(address->cells[0], 0, 1);
}


/* prefetchable bit p */

static unsigned
extract_p(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 1, 1);
}

static void
set_p(device_unit *address)
{
  BLIT32(address->cells[0], 1, 1);
}


/* aliased bit t */

static unsigned
extract_t(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 2, 2);
}

static void
set_t(device_unit *address)
{
  BLIT32(address->cells[0], 2, 1);
}


/* space code ss */

typedef enum {
  ss_config_code = 0,
  ss_io_code = 1,
  ss_32bit_memory_code = 2,
  ss_64bit_memory_code = 3,
} ss_type;

static ss_type
extract_ss(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 6, 7);
}

static void
set_ss(device_unit *address, ss_type val)
{
  MBLIT32(address->cells[0], 6, 7, val);
}


/* bus number bbbbbbbb */

#if 0
static unsigned
extract_bbbbbbbb(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 8, 15);
}
#endif

#if 0
static void
set_bbbbbbbb(device_unit *address, unsigned val)
{
  MBLIT32(address->cells[0], 8, 15, val);
}
#endif


/* device number ddddd */

static unsigned
extract_ddddd(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 16, 20);
}

static void
set_ddddd(device_unit *address, unsigned val)
{
  MBLIT32(address->cells[0], 16, 20, val);
}


/* function number fff */

static unsigned
extract_fff(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 21, 23);
}

static void
set_fff(device_unit *address, unsigned val)
{
  MBLIT32(address->cells[0], 21, 23, val);
}


/* register number rrrrrrrr */

static unsigned
extract_rrrrrrrr(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return EXTRACTED32(address->cells[0], 24, 31);
}

static void
set_rrrrrrrr(device_unit *address, unsigned val)
{
  MBLIT32(address->cells[0], 24, 31, val);
}


/* MSW of 64bit address hh..hh */

static unsigned
extract_hh_hh(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return address->cells[1];
}

static void
set_hh_hh(device_unit *address, unsigned val)
{
  address->cells[2] = val;
}


/* LSW of 64bit address ll..ll */

static unsigned
extract_ll_ll(const device_unit *address)
{
  ASSERT(address->nr_cells == 3);
  return address->cells[2];
}

static void
set_ll_ll(device_unit *address, unsigned val)
{
  address->cells[2] = val;
}


/* Convert PCI textual bus address into a device unit */

static int
hw_phb_unit_decode(device *me,
		   const char *unit,
		   device_unit *address)
{
  char *end = NULL;
  const char *chp = unit;
  unsigned long val;

  if (device_nr_address_cells(me) != 3)
    device_error(me, "PCI bus should have #address-cells == 3");
  memset(address, 0, sizeof(*address));

  if (unit == NULL)
    return 0;

  address->nr_cells = 3;