sem-switch.c

这个是LINUX下的GDB调度工具的源码

/* Simulator instruction semantics for m32rbf.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifdef DEFINE_LABELS

  /* The labels have the case they have because the enum of insn types
     is all uppercase and in the non-stdc case the insn symbol is built
     into the enum name.  */

  static struct {
    int index;
    void *label;
  } labels[] = {
    { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
    { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
    { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
    { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
    { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
    { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
    { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
    { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
    { M32RBF_INSN_AND, && case_sem_INSN_AND },
    { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
    { M32RBF_INSN_OR, && case_sem_INSN_OR },
    { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
    { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
    { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
    { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
    { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
    { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
    { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
    { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
    { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
    { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
    { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
    { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
    { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
    { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
    { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
    { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
    { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
    { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
    { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
    { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
    { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
    { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
    { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
    { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
    { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
    { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
    { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
    { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
    { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
    { M32RBF_INSN_REM, && case_sem_INSN_REM },
    { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
    { M32RBF_INSN_JL, && case_sem_INSN_JL },
    { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
    { M32RBF_INSN_LD, && case_sem_INSN_LD },
    { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
    { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
    { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
    { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
    { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
    { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
    { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
    { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
    { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
    { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
    { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
    { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
    { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
    { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
    { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
    { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
    { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
    { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
    { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
    { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
    { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
    { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
    { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
    { M32RBF_INSN_MV, && case_sem_INSN_MV },
    { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
    { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
    { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
    { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
    { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
    { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
    { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
    { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
    { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
    { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
    { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
    { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
    { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
    { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
    { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
    { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
    { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
    { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
    { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
    { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
    { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
    { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
    { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
    { M32RBF_INSN_ST, && case_sem_INSN_ST },
    { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
    { M32RBF_INSN_STB, && case_sem_INSN_STB },
    { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
    { M32RBF_INSN_STH, && case_sem_INSN_STH },
    { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
    { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
    { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
    { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
    { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
    { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
    { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
    { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
    { M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
    { M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW },
    { M32RBF_INSN_BSET, && case_sem_INSN_BSET },
    { M32RBF_INSN_BCLR, && case_sem_INSN_BCLR },
    { M32RBF_INSN_BTST, && case_sem_INSN_BTST },
    { 0, 0 }
  };
  int i;

  for (i = 0; labels[i].label != 0; ++i)
    {
#if FAST_P
      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
#else
      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
#endif
    }

#undef DEFINE_LABELS
#endif /* DEFINE_LABELS */

#ifdef DEFINE_SWITCH

/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
   off frills like tracing and profiling.  */
/* FIXME: A better way would be to have TRACE_RESULT check for something
   that can cause it to be optimized out.  Another way would be to emit
   special handlers into the instruction "stream".  */

#if FAST_P
#undef TRACE_RESULT
#define TRACE_RESULT(cpu, abuf, name, type, val)
#endif

#undef GET_ATTR
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
#else
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
#endif

{

#if WITH_SCACHE_PBB

/* Branch to next handler without going around main loop.  */
#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)

#else /* ! WITH_SCACHE_PBB */

#define NEXT(vpc) BREAK (sem)
#ifdef __GNUC__
#if FAST_P
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
#else
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
#endif
#else
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
#endif

#endif /* ! WITH_SCACHE_PBB */

    {

  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
    /* Update the recorded pc in the cpu state struct.
       Only necessary for WITH_SCACHE case, but to avoid the
       conditional compilation ....  */
    SET_H_PC (pc);
    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
       using the default-insn-bitsize spec.  When executing insns in parallel
       we may want to queue the fault and continue execution.  */
    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_AFTER) : /* --after-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
#if WITH_SCACHE_PBB_M32RBF
    m32rbf_pbb_after (current_cpu, sem_arg);
#endif
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_BEFORE) : /* --before-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
#if WITH_SCACHE_PBB_M32RBF
    m32rbf_pbb_before (current_cpu, sem_arg);
#endif
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
#if WITH_SCACHE_PBB_M32RBF
#ifdef DEFINE_SWITCH
    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
			       pbb_br_type, pbb_br_npc);
    BREAK (sem);
#else
    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
			       CPU_PBB_BR_TYPE (current_cpu),
			       CPU_PBB_BR_NPC (current_cpu));
#endif
#endif
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
#if WITH_SCACHE_PBB_M32RBF
    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH
    BREAK (sem);
#endif
#endif
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
#if WITH_SCACHE_PBB_M32RBF
#if defined DEFINE_SWITCH || defined FAST_P
    /* In the switch case FAST_P is a constant, allowing several optimizations
       in any called inline functions.  */
    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
#else
#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
#else
    vpc = m32rbf_pbb_begin (current_cpu, 0);
#endif
#endif
#endif
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_ADD) : /* add $dr,$sr */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

  {
    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {
    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_AND) : /* and $dr,$sr */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

  {
    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_and3.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {
    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_OR) : /* or $dr,$sr */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

  {
    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_and3.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {
    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

  {
    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_and3.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {
    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_addi.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

  {
    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
    * FLD (i_dr) = opval;
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */